{"id":2220944,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220944/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20260408091136.2794546-6-varadarajan.narayanan@oss.qualcomm.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260408091136.2794546-6-varadarajan.narayanan@oss.qualcomm.com>","date":"2026-04-08T09:11:32","name":"[v1,5/9] misc: qcom_geni: Add minicore support","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"77ca8685186e7fe2f267f415882e3b2c973ca4f7","submitter":{"id":92283,"url":"http://patchwork.ozlabs.org/api/1.1/people/92283/?format=json","name":"Varadarajan Narayanan","email":"varadarajan.narayanan@oss.qualcomm.com"},"delegate":{"id":151538,"url":"http://patchwork.ozlabs.org/api/1.1/users/151538/?format=json","username":"kcxt","first_name":"Casey","last_name":"Connolly","email":"casey.connolly@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20260408091136.2794546-6-varadarajan.narayanan@oss.qualcomm.com/mbox/","series":[{"id":499137,"url":"http://patchwork.ozlabs.org/api/1.1/series/499137/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=499137","date":"2026-04-08T09:11:27","name":"Qualcomm IPQ5210 SoC bringup","version":1,"mbox":"http://patchwork.ozlabs.org/series/499137/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220944/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220944/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=a5FE+3IW;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=jXnM3z3d;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)","phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com","phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de","phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"a5FE+3IW\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"jXnM3z3d\";\n\tdkim-atps=neutral","phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com","phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com"],"Received":["from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frNP00vJnz1yD3\n\tfor ; Wed, 08 Apr 2026 22:56:36 +1000 (AEST)","from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D5FF5841C2;\n\tWed, 8 Apr 2026 14:55:32 +0200 (CEST)","by phobos.denx.de (Postfix, from userid 109)\n id EBD0D838BB; Wed, 8 Apr 2026 11:12:50 +0200 (CEST)","from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 8E78280433\n for ; Wed, 8 Apr 2026 11:12:48 +0200 (CEST)","from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6387FwAM1619624\n for ; Wed, 8 Apr 2026 09:12:47 GMT","from mail-pl1-f197.google.com (mail-pl1-f197.google.com\n [209.85.214.197])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ddacrj12f-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Wed, 08 Apr 2026 09:12:46 +0000 (GMT)","by mail-pl1-f197.google.com with SMTP id\n d9443c01a7336-2b23c909256so83230125ad.0\n for ; Wed, 08 Apr 2026 02:12:46 -0700 (PDT)","from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b27478945asm260020325ad.28.2026.04.08.02.12.34\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 08 Apr 2026 02:12:44 -0700 (PDT)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2","DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:date:from:in-reply-to:message-id\n :mime-version:references:subject:to; s=qcppdkim1; bh=Hd1J7ilWQjg\n HnMbh7OnpDcRH8M1AtCS0O5VR04Xx2SQ=; b=a5FE+3IWNylC+MKbt7YYZMC67zm\n UOJpDCwqKJzBHmvbGUm6hLc8tWAxlxGPoBW8KygsrY/+gR8UnQzF091HqP9i1jyy\n eizqrKHXtyEe2qhXLrNPqGdPpdofyepnDiyBxvkLsvlX6Rvbe8FLxTlURUHEQlyR\n I6bnrpPGHvxbF0L2zGBZbd9IwLKLLXfhHtUU7JsWSKYppXJBV3RwHrGSaAHCHtmE\n STeeSJsSGgRp4+n8JXU4C0qW3LiCoqrutJWVUYDMPjGDt/zqDC82QcXdpQC0n90J\n z9dDEYSGCvVX7RDcr2NfvMJz/e5aJQEo5Bi4NM7ObPz1UU8tReeIVKq4mLA==","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775639566; x=1776244366; darn=lists.denx.de;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=Hd1J7ilWQjgHnMbh7OnpDcRH8M1AtCS0O5VR04Xx2SQ=;\n b=jXnM3z3dAWQmuIGaMtdQywpmgH0VbvR/ZlrzTDqRQjTXOaNVST2MAqTCGPAw6+NHm7\n o6dofZgT+JDyJ3w0jhjngKYtr9w0wLa23xmwtaUbr5lbu5t8hFBDln/EZQfoylChFxCo\n IPEzVwCrbeSbPoAkBZQEVNNvD3ZPG3cy0MbuYOBFFHhH+FQr/VRrwB9mQiImSLKKVHsT\n jYQ+iZP+4+QTq1e+LPED5c4xRF8Xwjqh6o9rrjvCLAdF9wzIeKNykLPfpL/1i+szDsyv\n j3iGqt4pqpLeEDLvyngoK1gT7+a2p0NXi5mW0s0N7oReWNMb9JyS1ZGVZHMbPI+wyf1p\n RrPA=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775639566; x=1776244366;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=Hd1J7ilWQjgHnMbh7OnpDcRH8M1AtCS0O5VR04Xx2SQ=;\n b=Qj6ZSe4IMRKcQupwZoJx2xMPJhlSGM5OzrU95/R6DwKTtCTTHXGqNWxLTWKlPMXrAB\n hLXYEK+FEusczQ7PDibpNZjNYgtBjh7TONtGZPEj8lb4GBSNA8s37IcVu+eZ+qtcwdv1\n ln6YM2jbNXP1OyG/TnfjB2XwPw56GwFYt7kKWD0pzXo3ow/DepRPoNxpp2v1P90saLQ3\n PfJUgLt4NYougCdUTIZ01/Qlt4ukk8chFgrq8ekbA0gkcPGrBMvJMvlukzovbAuOAvF+\n PG5H+ATjNi7g1nEntEg2OyYZfHrhlIU6x0nomUZMxlxnnkzhhjfhHXAZ+CG7mzC8YaKx\n RSRg==","X-Forwarded-Encrypted":"i=1;\n AJvYcCVvLjJLCdK5CTJRye7FlPETsHYsF0wOCIHTbnHWl6JbAHklcKzyeLcVp/Gj2UH3OFuD2c0Z7/o=@lists.denx.de","X-Gm-Message-State":"AOJu0YxhVCfMv+Va0dSJjKK44Xal6A1Ce0e9JItBpyYcsB8RNGY/Ygnu\n ffztYe5+3xJoHgAMyPaMmr9P7BXF9SqJPVeOuqZFpsi1bo9GSfJwcU+aZwAHVfcj2FQQW+Q1L0W\n +Ntg6INZS7FJd7+cMyJYGF3uRNnhB+Q/KLtNn6nMR5vNDEXJ1bp0wYX5w","X-Gm-Gg":"AeBDievzPdvJNP3AvqHow7vEdm6f9iwUoAu8EYYBMe2m3Ozj4lR6vWN5HL+dcu5kV5W\n Nt3ATpinrQ5HG6cFMDKICA6d2s+PBsQKrXuKxzLwW5Fx97zcJjn+07hBTWPp0rY5glDw3W/fvvi\n c4MJHihWnfUKHl/5e+TvpQpOBHBiQXd05wTUxyKFzIu7YOvXIHH1beOy6ZaYy/5l0lWnpkrXI1/\n B6bd1UL4dpSXl8AKdYCSO+efFPWe/0x2DW40QFwTzOzrq1takV9qJJb7a9eDHKzwlceHinkIsmI\n Tw0WjfoEExzfwyRy/jCxB3RWDa37r/ljJ1RhBWQv2Dsq9JDUTD4tN7LMFpP78Uf/y9f8RlziB74\n L9b+4JYZQsvJ1UYzIJVVJ7/c8UN7QqL6yQFGoRcWnOoePyPrMCgLDxQcukhxkejCPV9tyBValkU\n mhcSqAiw49+a0M3W1I3vKXcSDfo644/Ywc7LiyN+oiNsPI8engIzM=","X-Received":["by 2002:a17:903:950:b0:2ae:b991:a46f with SMTP id\n d9443c01a7336-2b2817f1a38mr241471415ad.42.1775639565771;\n Wed, 08 Apr 2026 02:12:45 -0700 (PDT)","by 2002:a17:903:950:b0:2ae:b991:a46f with SMTP id\n d9443c01a7336-2b2817f1a38mr241470585ad.42.1775639565212;\n Wed, 08 Apr 2026 02:12:45 -0700 (PDT)"],"From":"Varadarajan Narayanan ","To":"rayagonda.kokatanur@broadcom.com, trini@konsulko.com,\n casey.connolly@linaro.org, neil.armstrong@linaro.org,\n sumit.garg@kernel.org, peng.fan@nxp.com, jh80.chung@samsung.com,\n lukma@denx.de, anshuld@ti.com, tingting.meng@altera.com,\n alif.zakuan.yuslaimi@altera.com, alice.guo@nxp.com,\n quentin.schulz@cherry.de, ilias.apalodimas@linaro.org,\n varadarajan.narayanan@oss.qualcomm.com, xypron.glpk@gmx.de,\n mkorpershoek@kernel.org, afd@ti.com, andre.przywara@arm.com,\n h-salunke@ti.com, dario.binacchi@amarulasolutions.com, ye.li@nxp.com,\n dinesh.maniyam@altera.com, danila@jiaxyga.com, adrian@mainlining.org,\n luca.weiss@fairphone.com, balaji.selvanathan@oss.qualcomm.com,\n aswin.murugan@oss.qualcomm.com, david.wronek@mainlining.org,\n alexeymin@postmarketos.org, james.hilliard1@gmail.com,\n philip.molloy@analog.com, miquel.raynal@bootlin.com,\n malysagreg@gmail.com, richard.genoud@bootlin.com, sughosh.ganu@arm.com,\n u-boot@lists.denx.de, u-boot-qcom@groups.io","Cc":"snlakshm@qti.qualcomm.com, gopinath.sekar@oss.qualcomm.com","Subject":"[PATCH v1 5/9] misc: qcom_geni: Add minicore support","Date":"Wed, 8 Apr 2026 14:41:32 +0530","Message-Id":"<20260408091136.2794546-6-varadarajan.narayanan@oss.qualcomm.com>","X-Mailer":"git-send-email 2.34.1","In-Reply-To":"<20260408091136.2794546-1-varadarajan.narayanan@oss.qualcomm.com>","References":"<20260408091136.2794546-1-varadarajan.narayanan@oss.qualcomm.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Proofpoint-ORIG-GUID":"_0_qi3HTFErYpwHsS_EL2cXptFgZhidR","X-Proofpoint-GUID":"_0_qi3HTFErYpwHsS_EL2cXptFgZhidR","X-Authority-Analysis":"v=2.4 cv=WZs8rUhX c=1 sm=1 tr=0 ts=69d61c0e cx=c_pps\n a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8\n a=c6PXgn3fiFxYvSzRRRIA:9 a=1OuFwYUASf3TG4hYMiVC:22","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA4MDA4MiBTYWx0ZWRfX/eRB498md4o6\n Bfg7n7Y5AY0gLKsMIzJptKzrqlKLpT0hoM3togzxaK93nwYMo4Ye2v2PmIgRhVADFTGSJljm1O5\n w+Z55KGs7yAyhWAXQjlctdZ0QITfB8dBe/l8Oz/cw7KBwTIofi7RF8Z/Zbgs3gQyyE2XwtGNlPp\n TOTl9Ow+gFQpgHZjmvwUo/1cVml7JYBleErPkrcqxCy0EbAitF+wq8EwQ6nwFcxC7Zp2hMhx7ht\n XFapg0LS2HZ3yqvOquVs0rWo3MXdWkNAjBlNdPpd3mid/d9FSai1INmt/kNJtfsjM0AGfaw8MqJ\n /lyZ4xjnLaZMKj8wzSpom+WpHvsZEVlRnI6Qje0WfhnlLUK1OxK8xaeMEIT0fNAnzDImPW+MXLm\n JvHW403JcZjthjo13mDhOK83fjwSnLoHRDwMb9fHhShzaHcJZ7ZvcV6Mh/FufAjpo4X0DkZVgXU\n rMT0vcMmW7XWjQaMyUg==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-08_03,2026-04-08_01,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 clxscore=1011\n bulkscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 impostorscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080082","X-Mailman-Approved-At":"Wed, 08 Apr 2026 14:55:29 +0200","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.8 at phobos.denx.de","X-Virus-Status":"Clean"},"content":"The qcom_geni driver reads an ELF from storage and configures a set of\nregisters and programs the firmware to the GENI Serial Engine (GENI-SE)\nwrapper device for the expected functionality.\n\nUnlike the GENI-SE wrapper found in MSM SoCs, the IPQ5210's GENI-SE\nwrapper is pre-configured for one of the functions defined in 'enum\ngeni_se_protocol_type'. Hence, the firmware download is not needed.\nOnly the register configuration part is needed.\n\nEarlier, the boot stages before U-Boot would configure the GENI-SE (to\naccess UART/SPI etc). Since for IPQ5210 U-Boot SPL, the previous stage\n(i.e. boot ROM) doesn't do that modify the driver to do the register\nconfiguration part alone without reading an ELF from the storage.\n\nSigned-off-by: Varadarajan Narayanan \n---\n drivers/misc/qcom_geni.c | 168 ++++++++++++++++++++++++++++++---\n include/soc/qcom/geni-se.h | 5 +\n include/soc/qcom/qup-fw-load.h | 15 +++\n 3 files changed, 175 insertions(+), 13 deletions(-)","diff":"diff --git a/drivers/misc/qcom_geni.c b/drivers/misc/qcom_geni.c\nindex a62ae6a2478..d02ea804c33 100644\n--- a/drivers/misc/qcom_geni.c\n+++ b/drivers/misc/qcom_geni.c\n@@ -34,6 +34,102 @@ struct qup_se_rsc {\n \n struct geni_se_plat {\n \tbool need_firmware_load;\n+\tbool is_mini_core;\n+};\n+\n+/*\n+ * Register configuration for the QUP minicores to setup the corresponding\n+ * functionality of SPI/I2C/UART.\n+ */\n+static u8 cfg_reg_idx[] = {\n+\t/* 0 to 18 */\n+\t0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,\n+\t/* 64 to 113 */\n+\t64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80,\n+\t81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\n+\t98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,\n+\t112, 113,\n+};\n+\n+static u32 spi_cfg_val[] = {\n+\t/* 0 to 18 */\n+\t0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00240E78, 0x00011088,\n+\t0x00240007, 0x00000000, 0x00000000, 0x0001000A, 0x00000300, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00154400, 0x001483A0, 0x00AA8128, 0x00641002,\n+\t0x00004000,\n+\t/* 64 to 113 */\n+\t0x00000201, 0x0001FE05, 0x0002C2E7, 0x0A435C00, 0x0010011A, 0x08800000,\n+\t0x00000000, 0x100CAC00, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000018E4, 0x00000000,\n+\t0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x0007F807, 0x000FFEFE, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00200000, 0x00000004, 0x00000009, 0x0007F807, 0x000FFEFE, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00C0033F, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000055,\n+};\n+\n+static u32 uart_cfg_val[] = {\n+\t/* 0 to 18 */\n+\t0x00000024, 0x00000000, 0x00000024, 0x00000000, 0x00019A00, 0x00400000,\n+\t0x00E00000, 0x00010020, 0x00000000, 0x00000000, 0x00000300, 0x00000700,\n+\t0x00000400, 0x00000000, 0x00000000, 0x00C00000, 0x00000000, 0x00C00024,\n+\t0x00000B00,\n+\t/* 64 to 113 */\n+\t0x00020231, 0x0000CE05, 0x000360E7, 0x0941E6A8, 0x00100510, 0x42C01E51,\n+\t0x00000401, 0x002E8400, 0x1694581A, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x0000031C, 0x00000000,\n+\t0x0000000F, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00081C06, 0x00004010, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x0000000D, 0x00000000, 0x00081C06, 0x00004010, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00C02415, 0x0000000E, 0x00000001,\n+\t0x00000001, 0x00000000, 0x00C00000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000055,\n+};\n+\n+static u32 i2c_cfg_val[] = {\n+\t/* 0 to 18 */\n+\t0x00000090, 0x00000000, 0x00000090, 0x00000000, 0x00038028, 0x00084080,\n+\t0x00000343, 0x00010000, 0x00000000, 0x00001A00, 0x00000100, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00808008, 0x001C0020, 0x00000000, 0x00020000,\n+\t0x00000000,\n+\t/* 64 to 113 */\n+\t0x00000201, 0x0001FC01, 0x00036222, 0x09C01FFC, 0x00100120, 0x02C00000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000409, 0x00000003,\n+\t0x00000002, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x0007F8FE, 0x000FFEFE, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000001, 0x0007F807, 0x000FFEFE, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000000, 0x00C00000, 0x00000000, 0x00000000, 0x00000000,\n+\t0x00000000, 0x00000055,\n+};\n+\n+static struct qup_mini_core_info qup_mini_cores[] = {\n+\t{\n+\t\t.serial_protocol = GENI_SE_SPI,\n+\t\t.fw_version = 0xb02,\n+\t\t.cfg_version = 0x9,\n+\t\t.cfg_count = ARRAY_SIZE(spi_cfg_val),\n+\t\t.cfg_val = spi_cfg_val,\n+\t\t.cfg_idx = cfg_reg_idx,\n+\t}, {\n+\t\t.serial_protocol = GENI_SE_UART,\n+\t\t.fw_version = 0x405,\n+\t\t.cfg_version = 0xa,\n+\t\t.cfg_count = ARRAY_SIZE(uart_cfg_val),\n+\t\t.cfg_val = uart_cfg_val,\n+\t\t.cfg_idx = cfg_reg_idx,\n+\t}, {\n+\t\t.serial_protocol = GENI_SE_I2C,\n+\t\t.fw_version = 0x204,\n+\t\t.cfg_version = 0x9,\n+\t\t.cfg_count = ARRAY_SIZE(i2c_cfg_val),\n+\t\t.cfg_val = i2c_cfg_val,\n+\t\t.cfg_idx = cfg_reg_idx,\n+\t}, {\n+\t\t.serial_protocol = GENI_SE_INVALID_PROTO,\n+\t},\n };\n \n /**\n@@ -163,16 +259,38 @@ static void geni_config_common_control(struct qup_se_rsc *rsc)\n \t\t COMMON_CSR_SLV_CLK_CGC_ON_BMASK);\n }\n \n-static int load_se_firmware(struct qup_se_rsc *rsc, struct elf_se_hdr *hdr)\n+static int load_se_firmware(struct qup_se_rsc *rsc, int elf, void *info)\n {\n+\tstruct elf_se_hdr *hdr, tmp_hdr;\n \tconst u32 *fw_val_arr, *cfg_val_arr;\n \tconst u8 *cfg_idx_arr;\n \tu32 i, reg_value, mask, ramn_cnt;\n \tint ret;\n \n-\tfw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);\n-\tcfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;\n-\tcfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);\n+\tif (elf) {\n+\t\thdr = info;\n+\t\tfw_val_arr = (const u32 *)((u8 *)hdr + hdr->fw_offset);\n+\t\tcfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset;\n+\t\tcfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset);\n+\t} else {\n+\t\tstruct qup_mini_core_info *qmc = info;\n+\n+\t\tfor (; qmc->serial_protocol != GENI_SE_INVALID_PROTO; qmc++)\n+\t\t\tif (qmc->serial_protocol == rsc->protocol)\n+\t\t\t\tbreak;\n+\n+\t\ttmp_hdr.magic = MAGIC_NUM_SE;\n+\t\ttmp_hdr.version = 1;\n+\t\ttmp_hdr.serial_protocol = rsc->protocol;\n+\t\ttmp_hdr.fw_version = qmc->fw_version;\n+\t\ttmp_hdr.cfg_version = qmc->cfg_version;\n+\t\ttmp_hdr.fw_size_in_items = qmc->cfg_ram_count;\n+\t\ttmp_hdr.cfg_size_in_items = qmc->cfg_count;\n+\t\thdr = &tmp_hdr;\n+\t\tfw_val_arr = (const u32 *)qmc->cfg_ram;\n+\t\tcfg_idx_arr = (const u8 *)qmc->cfg_idx;\n+\t\tcfg_val_arr = (const u32 *)qmc->cfg_val;\n+\t}\n \n \tgeni_config_common_control(rsc);\n \n@@ -350,8 +468,8 @@ int qcom_geni_load_firmware(phys_addr_t qup_base,\n {\n \tstruct qup_se_rsc rsc;\n \tstruct elf_se_hdr *hdr;\n-\tint ret;\n-\tvoid *fw;\n+\tint ret, elf;\n+\tvoid *fw, *info;\n \n \trsc.dev = dev;\n \trsc.base = qup_base;\n@@ -377,15 +495,22 @@ int qcom_geni_load_firmware(phys_addr_t qup_base,\n \t/* The firmware blob is the private data of the GENI wrapper (parent) */\n \tfw = dev_get_priv(dev->parent);\n \n-\tret = read_elf(&rsc, fw, &hdr);\n-\tif (ret) {\n-\t\tdev_err(dev, \"Failed to read ELF: %d\\n\", ret);\n-\t\treturn ret;\n+\tif (IS_ELF(*(Elf32_Ehdr *)fw)) {\n+\t\tret = read_elf(&rsc, fw, &hdr);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to read ELF: %d\\n\", ret);\n+\t\t\treturn ret;\n+\t\t}\n+\t\telf = 1;\n+\t\tinfo = hdr;\n+\t} else {\n+\t\telf = 0;\n+\t\tinfo = fw;\n \t}\n \n \tdev_info(dev, \"Loading QUP firmware...\\n\");\n \n-\treturn load_se_firmware(&rsc, hdr);\n+\treturn load_se_firmware(&rsc, elf, info);\n }\n \n /*\n@@ -414,6 +539,9 @@ static int geni_se_of_to_plat(struct udevice *dev)\n \n \t\tif (proto == GENI_SE_INVALID_PROTO)\n \t\t\tplat->need_firmware_load = true;\n+\n+\t\tif (readl(res.start + QUPV3_SE_HW_PARAM_2) & GEN_USE_MINICORES)\n+\t\t\tplat->is_mini_core = true;\n \t}\n \n \treturn 0;\n@@ -473,7 +601,7 @@ static int probe_children_load_firmware(struct udevice *dev)\n \t\tret = 0;\n \t\t/* Find the device for this ofnode, or bind it */\n \t\tif (device_find_global_by_ofnode(child, &child_dev))\n-\t\t\tret = lists_bind_fdt(dev, child, &child_dev, NULL, false);\t\n+\t\t\tret = lists_bind_fdt(dev, child, &child_dev, NULL, false);\n \t\tif (ret) {\n \t\t\t/* Skip nodes that don't have drivers */\n \t\t\tdebug(\"Failed to probe child %s: %d\\n\", ofnode_get_name(child), ret);\n@@ -492,7 +620,11 @@ static int probe_children_load_firmware(struct udevice *dev)\n * Load firmware for QCOM GENI peripherals from the dedicated partition on storage and bind/probe\n * all the peripheral devices that need firmware to be loaded.\n */\n-static int qcom_geni_fw_initialise(void)\n+#if CONFIG_XPL_BUILD\n+int qcom_geni_fw_initialise(struct udevice *dev)\n+#else\n+int qcom_geni_fw_initialise(void)\n+#endif\n {\n \tdebug(\"Loading firmware for QCOM GENI SE\\n\");\n \tstruct udevice *geni_wrapper, *blk_dev;\n@@ -520,6 +652,10 @@ static int qcom_geni_fw_initialise(void)\n \n \tret = find_qupfw_part(&blk_dev, &part_info);\n \tif (ret) {\n+\t\tif (plat->is_mini_core) {\n+\t\t\tfw_buf = qup_mini_cores;\n+\t\t\tgoto mini_core;\n+\t\t}\n \t\tpr_err(\"QUP firmware partition not found\\n\");\n \t\treturn 0;\n \t}\n@@ -544,6 +680,7 @@ static int qcom_geni_fw_initialise(void)\n \t\treturn 0;\n \t}\n \n+mini_core:\n \t/*\n \t * OK! Firmware is loaded, now bind and probe remaining children. They will attempt to load\n \t * firmware during probe. Do this for each GENI SE wrapper that needs firmware loading.\n@@ -563,7 +700,9 @@ static int qcom_geni_fw_initialise(void)\n \treturn 0;\n }\n \n+#if !CONFIG_XPL_BUILD\n EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, qcom_geni_fw_initialise);\n+#endif\n \n static const struct udevice_id geni_ids[] = {\n \t{ .compatible = \"qcom,geni-se-qup\" },\n@@ -577,4 +716,7 @@ U_BOOT_DRIVER(geni_se_qup) = {\n \t.of_to_plat = geni_se_of_to_plat,\n \t.plat_auto = sizeof(struct geni_se_plat),\n \t.flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,\n+#if CONFIG_XPL_BUILD\n+\t.probe = qcom_geni_fw_initialise,\n+#endif\n };\ndiff --git a/include/soc/qcom/geni-se.h b/include/soc/qcom/geni-se.h\nindex fc9a8e82cd8..e51dd06fa94 100644\n--- a/include/soc/qcom/geni-se.h\n+++ b/include/soc/qcom/geni-se.h\n@@ -77,6 +77,7 @@ enum geni_se_protocol_type {\n #define SE_IRQ_EN\t\t\t0xe1c\n #define SE_HW_PARAM_0\t\t\t0xe24\n #define SE_HW_PARAM_1\t\t\t0xe28\n+#define SE_HW_PARAM_2\t\t\t0xe2c\n #define SE_DMA_GENERAL_CFG\t\t0xe30\n \n /* GENI_DFS_IF_CFG fields */\n@@ -248,6 +249,10 @@ enum geni_se_protocol_type {\n /* SE_HW_PARAM_0 fields */\n #define TX_FIFO_WIDTH_MSK\t\tGENMASK(29, 24)\n #define TX_FIFO_WIDTH_SHFT\t\t24\n+\n+/* SE_HW_PARAM_2 fields */\n+#define GEN_USE_MINICORES\t\tBIT(12)\n+\n /*\n * For QUP HW Version >= 3.10 Tx fifo depth support is increased\n * to 256bytes and corresponding bits are 16 to 23\ndiff --git a/include/soc/qcom/qup-fw-load.h b/include/soc/qcom/qup-fw-load.h\nindex a67a93c72a4..a3ae4122681 100644\n--- a/include/soc/qcom/qup-fw-load.h\n+++ b/include/soc/qcom/qup-fw-load.h\n@@ -14,6 +14,7 @@\n #define GENI_INIT_CFG_REVISION\t\t0x0\n #define GENI_S_INIT_CFG_REVISION\t0x4\n #define GENI_FORCE_DEFAULT_REG\t\t0x20\n+#define GENI_OUTPUT_CTRL\t\t0x24\n #define GENI_CGC_CTRL\t\t\t0x28\n #define GENI_CFG_REG0\t\t\t0x100\n \n@@ -21,6 +22,9 @@\n #define RX_FIFO_WIDTH_BIT\t\t24\n #define RX_FIFO_WIDTH_MASK\t\t0x3F\n \n+#define QUPV3_SE_HW_PARAM_2\t\t0xe2c\n+#define GEN_USE_MINICORES\t\tBIT(12)\n+\n /*Same registers as GENI_DMA_MODE_EN*/\n #define QUPV3_SE_GENI_DMA_MODE_EN\t0x258\n #define GENI_M_IRQ_ENABLE\t\t0x614\n@@ -173,6 +177,17 @@ struct elf_se_hdr {\n \n struct udevice;\n \n+struct qup_mini_core_info {\n+\tu16 serial_protocol;\n+\tu16 fw_version;\n+\tu16 cfg_version;\n+\tu16 cfg_count;\n+\tu32 *cfg_val;\n+\tu8 *cfg_idx;\n+\tu32 *cfg_ram;\n+\tu32 cfg_ram_count;\n+};\n+\n int qcom_geni_load_firmware(phys_addr_t qup_base, struct udevice *dev);\n \n #endif /* _LINUX_QCOM_QUP_FW_LOAD */\n","prefixes":["v1","5/9"]}