{"id":2220873,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220873/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260408-clk-pwm-gpio-v2-1-d22f1f3498a0@radxa.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.1/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408-clk-pwm-gpio-v2-1-d22f1f3498a0@radxa.com>","date":"2026-04-08T10:07:32","name":"[v2,1/2] dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"8ca74828017327ffb61d6a1afd66cbec8f0d0b6f","submitter":{"id":90715,"url":"http://patchwork.ozlabs.org/api/1.1/people/90715/?format=json","name":"Xilin Wu","email":"sophon@radxa.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/patch/20260408-clk-pwm-gpio-v2-1-d22f1f3498a0@radxa.com/mbox/","series":[{"id":499115,"url":"http://patchwork.ozlabs.org/api/1.1/series/499115/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=499115","date":"2026-04-08T10:07:31","name":"pwm: clk-pwm: Add GPIO support for constant output levels","version":2,"mbox":"http://patchwork.ozlabs.org/series/499115/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220873/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220873/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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Wed, 08 Apr 2026 18:07:45 +0800 (CST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775642915; cv=none;\n b=bqmx6eWOOvWYEgnAsk5AvLo2F7qHK7QOTlb3O+mN7rqnzH+f9skpmp0dsMz8tSYSmUgdZCYpiix742F+hG+Zjaj7t6K9z2ibtV8hHPqI2BaCWLBWrMGnT8KqWiTU9GL81teDzL4UF2J1bPK/71BgMaHbA/SreB2bARQBWDbDDow=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775642915; c=relaxed/simple;\n\tbh=hyoSGNKO8z6d1axQ29oBEAL7xl1kP5y9LqcBAulHLMQ=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=GlhXrLFl7kwZpqY/42HDdmQoCaPfo8yWM3igBtca0DkqScM9pGSa1lm79cb9lrCxPzTNtPDpFmI7CkLwqTmudtDX7i95sVQA+0XgH7YOgZkUfFRXr/G/h5jGgvOBChsNKpDg9itIdMWFbL8Pku/qGw5NTp1yYhJXwV6++6QLCN0=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=radxa.com;\n spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=52.59.177.22","X-QQ-mid":"zesmtpsz5t1775642866t6935ec97","X-QQ-Originating-IP":"4qODUJGb35PW82fgR5f0LCmXadzWoz4xrJ1L5pcMYPQ=","X-QQ-SSF":"0000000000000000000000000000000","X-QQ-GoodBg":"0","X-BIZMAIL-ID":"12296274181211464006","EX-QQ-RecipientCnt":"10","From":"Xilin Wu ","Date":"Wed, 08 Apr 2026 18:07:32 +0800","Subject":"[PATCH v2 1/2] dt-bindings: pwm: clk-pwm: add optional GPIO and\n pinctrl properties","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260408-clk-pwm-gpio-v2-1-d22f1f3498a0@radxa.com>","References":"<20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com>","In-Reply-To":"<20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com>","To":"=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= ,\n Rob Herring , Krzysztof Kozlowski ,\n Conor Dooley , Nikita Travkin ","Cc":"linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n Xilin Wu ","X-Mailer":"b4 0.15.1","X-Developer-Signature":"v=1; a=openpgp-sha256; l=2512; i=sophon@radxa.com;\n h=from:subject:message-id; bh=hyoSGNKO8z6d1axQ29oBEAL7xl1kP5y9LqcBAulHLMQ=;\n b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJnXNN7tfMb07W11zRRXxo6iZPGW6CMH153PYW5f+LO+d\n EL4SqspHaUsDGJcDLJiiiwK8Qxz2Stzrz0VK9WDmcPKBDKEgYtTACZSsJKRYf6DAzsys7caqdZY\n 2kQncL+cU6uf2DJ9gejd3QuPidf9qmZk6Nk0U7Ds+H+VFKUDKZe21dq1STLF2n349/H+d1W3R28\n 1eAE=","X-Developer-Key":"i=sophon@radxa.com; a=openpgp;\n fpr=205F009D07796DD6E516752E32C31567AD9E324E","X-QQ-SENDSIZE":"520","Feedback-ID":"zesmtpsz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0","X-QQ-XMAILINFO":"N8r2YJN/ffrjkob54fqR58thY4A5iwbaYUjMjFmkKQCx3HXYzDhzaaGa\n\tZAtQq5IYnwTQb5DZRPvhrkelCsRvCXFs3zbXmbgyc+JqxeRvalRcwCZ2ejudG6y/dB9ZVYl\n\tExRQvOcedBy9t/THaoNDgoF73SGGOxEWGbrAK6fQqg9madUAKdZuCzcrk4zLxsw+BW71HQy\n\teIs/dk2WcI0Yy2CgG18lIilrZfPTrojkSrsxWBNKAnAB2+rngP2jvxbuUU/djTlIQJ8PD9q\n\tAUkBlBoBS9d7TfE2FB8tFOplzOcEHDp/zcZeWnZ1pweEOI1vLUtDBb6GxORc0N0rtR6hCgf\n\tEoj9KcciX9lDXJliAngN63b40PsAHSXhMXi7vC0iLG6UgnlfSGBpdOCd+8r54pdeXgg1Xt2\n\tF5hA5hG+9c5iemgEFUzE9ngVOXPi6Y2A1uEeVVjMPkfVnKQdALidp/lFUj5KaP7v5PjV42y\n\tFhMnd9WGDVkqfP5cVrN8ovhb0yGkC/HUivo0xu5CHFHTs9lVW4LbdONtVE8DdCChesuQ5ZM\n\tyXoIno/dZ/FIn3TZVn0gF0W3C5zGRHBju0JWZRABxs/06hwoOQIQ6/oH9IUwKQqJXpae0tn\n\tLhvxDqI4QAnYSQvGfSIu8q9bnlJALV1j4OpDQrxd4oJIj/35TYZknjrZ6izLWrBX+Wp5caQ\n\tLs9/Pif5i2zdRgkGnH1BaXpGgyyYZiyXKy6NYAkgUmjc1bRX7t22nupv5iLKHaz7hbJeJh3\n\t0GydDhw2sQfq5zE04pEMitrWbElLGMHuXDCjSgKuXV6doB2wsC5WPy7VYJyNXmh/1RYDhO7\n\t7Ts5RisMU/uXyU2kFoWdrdVUw4EZ/PG53ByX+mpE2/6I9PaMXTq4T7CZwITZeuKkZs25E5U\n\tCs7gRY1iSDWrFPLm73edyUvaoLL8+5/hhPOMGNXSuYGmK8xtd0pmnIhLajbj9X7rB6XWMWZ\n\tXuRCVy9wB3QmhwYEq2qzIUoHtj5xJ64NydVxK5z5fzfnM8dSDh2RaPeEtd47hd+fRhZcbZk\n\tj29jsOHpCmys/+3VvbUzmdJl4iRa5r/lm9jHf97ECTC+F7tcF6","X-QQ-XMRINFO":"OWPUhxQsoeAVwkVaQIEGSKwwgKCxK/fD5g==","X-QQ-RECHKSPAM":"0"},"content":"The clk-pwm driver cannot produce constant output levels (0% or 100%\nduty cycle, or disabled state) through the clock hardware alone - the\nactual pin level when the clock is off is undefined and\nhardware-dependent.\n\nDocument optional gpios, pinctrl-names, pinctrl-0, and pinctrl-1\nproperties that allow the driver to switch the pin between clock\nfunction mux (for normal PWM output) and GPIO mode (to drive a\ndeterministic constant level).\n\nSigned-off-by: Xilin Wu \n---\n Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 +++++++++++++++++++++-\n 1 file changed, 35 insertions(+), 1 deletion(-)","diff":"diff --git a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml\nindex ec1768291503..2a0e3e02d27b 100644\n--- a/Documentation/devicetree/bindings/pwm/clk-pwm.yaml\n+++ b/Documentation/devicetree/bindings/pwm/clk-pwm.yaml\n@@ -15,6 +15,11 @@ description: |\n It's often possible to control duty-cycle of such clocks which makes them\n suitable for generating PWM signal.\n \n+ Optionally, a GPIO and pinctrl states can be provided. When a constant\n+ output level is needed (0%, 100%, or disabled), the pin is switched to\n+ GPIO mode to drive the level directly. For normal PWM output the pin is\n+ switched back to its clock function mux.\n+\n allOf:\n - $ref: pwm.yaml#\n \n@@ -29,6 +34,26 @@ properties:\n \"#pwm-cells\":\n const: 2\n \n+ gpios:\n+ description:\n+ Optional GPIO used to drive a constant level when the PWM output is\n+ disabled or set to 0% / 100% duty cycle. When provided, pinctrl states\n+ \"default\" (clock mux) and \"gpio\" must also be defined.\n+ maxItems: 1\n+\n+ pinctrl-names: true\n+\n+ pinctrl-0:\n+ description: Pin configuration for clock function mux (normal PWM).\n+ maxItems: 1\n+\n+ pinctrl-1:\n+ description: Pin configuration for GPIO mode (constant level output).\n+ maxItems: 1\n+\n+dependencies:\n+ gpios: [ pinctrl-0, pinctrl-1 ]\n+\n unevaluatedProperties: false\n \n required:\n@@ -41,6 +66,15 @@ examples:\n compatible = \"clk-pwm\";\n #pwm-cells = <2>;\n clocks = <&gcc 0>;\n- pinctrl-names = \"default\";\n+ };\n+\n+ - |\n+ pwm {\n+ compatible = \"clk-pwm\";\n+ #pwm-cells = <2>;\n+ clocks = <&gcc 0>;\n+ pinctrl-names = \"default\", \"gpio\";\n pinctrl-0 = <&pwm_clk_flash_default>;\n+ pinctrl-1 = <&pwm_clk_flash_gpio>;\n+ gpios = <&tlmm 32 0>;\n };\n","prefixes":["v2","1/2"]}