{"id":2220790,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220790/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-11-54b4736a1e77@gmail.com/","project":{"id":70,"url":"http://patchwork.ozlabs.org/api/1.1/projects/70/?format=json","name":"Linux KVM RISC-V","link_name":"kvm-riscv","list_id":"kvm-riscv.lists.infradead.org","list_email":"kvm-riscv@lists.infradead.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260407-riscv_insn_table-v1-11-54b4736a1e77@gmail.com>","date":"2026-04-08T04:45:59","name":"[11/16] riscv: kvm: Use generated instruction headers for mmio emulation","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"29a6011cbe32b1ae7ad88d69776d7a239b76bbd7","submitter":{"id":92521,"url":"http://patchwork.ozlabs.org/api/1.1/people/92521/?format=json","name":"Charlie Jenkins via B4 Relay","email":"devnull+thecharlesjenkins.gmail.com@kernel.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-11-54b4736a1e77@gmail.com/mbox/","series":[{"id":499063,"url":"http://patchwork.ozlabs.org/api/1.1/series/499063/?format=json","web_url":"http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=499063","date":"2026-04-08T04:45:48","name":"riscv: Generate riscv instruction functions","version":1,"mbox":"http://patchwork.ozlabs.org/series/499063/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220790/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220790/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=21ON2S1H;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Tx3nmzri;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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a=ed25519-sha256; t=1775623594; l=8840;\n i=thecharlesjenkins@gmail.com; s=2026030; h=from:subject:message-id;\n bh=/UVDQrQUvbZ5aOgH8m1pSV2EuBX5B263I5vQY5SYago=;\n b=2HmEIVg9U6gaVnKq9aREtjrfTpOCkBdKmi1N5IKel6R8t3TNnM+d2/vvewRkS4i8HeULN99mu\n wc5BI2x2Y1TCxqBWTYmdg0F5JUiOA23t3o9g8BVjZVg1FxEghmBY89a","X-Developer-Key":"i=thecharlesjenkins@gmail.com; a=ed25519;\n pk=vpF2USrG+aB6CTbSt34rzJKsAVe/l+GAXo1IomCMETk=","X-Endpoint-Received":"by B4 Relay for thecharlesjenkins@gmail.com/2026030\n with auth_id=663","X-Original-From":"Charlie Jenkins ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20260407_214640_769711_4C75784E ","X-CRM114-Status":"GOOD ( 16.76 )","X-Spam-Score":"-0.0 (/)","X-Spam-Report":"Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Charlie Jenkins Migrate the mmio emulation code to\n use\n the generated instruction headers instead of the hand-written instruction\n composition functions. Signed-off-by: Charlie Jenkins ---\n arch/riscv/include/asm/kvm_vcpu_insn.h\n | 2 +- arch/riscv/kvm/vcpu_insn.c | 127 ++++++++++++++ 2 files changed, 55\n insertions(+), 74 deletions(-)\n Content analysis details: (-0.0 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 2.1 FREEMAIL_FORGED_REPLYTO Freemail in Reply-To, but not From","X-BeenThere":"kvm-riscv@lists.infradead.org","X-Mailman-Version":"2.1.34","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Reply-To":"thecharlesjenkins@gmail.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"kvm-riscv\" ","Errors-To":"kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"From: Charlie Jenkins \n\nMigrate the mmio emulation code to use the generated instruction headers\ninstead of the hand-written instruction composition functions.\n\nSigned-off-by: Charlie Jenkins \n---\n arch/riscv/include/asm/kvm_vcpu_insn.h | 2 +-\n arch/riscv/kvm/vcpu_insn.c | 127 ++++++++++++++-------------------\n 2 files changed, 55 insertions(+), 74 deletions(-)","diff":"diff --git a/arch/riscv/include/asm/kvm_vcpu_insn.h b/arch/riscv/include/asm/kvm_vcpu_insn.h\nindex 350011c83581..106fb4c45108 100644\n--- a/arch/riscv/include/asm/kvm_vcpu_insn.h\n+++ b/arch/riscv/include/asm/kvm_vcpu_insn.h\n@@ -11,7 +11,7 @@ struct kvm_run;\n struct kvm_cpu_trap;\n \n struct kvm_mmio_decode {\n-\tunsigned long insn;\n+\tunsigned long rd;\n \tint insn_len;\n \tint len;\n \tint shift;\ndiff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c\nindex 311e2530f888..1d8741d02242 100644\n--- a/arch/riscv/kvm/vcpu_insn.c\n+++ b/arch/riscv/kvm/vcpu_insn.c\n@@ -376,7 +376,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\t\t unsigned long htinst)\n {\n \tu8 data_buf[8];\n-\tunsigned long insn;\n+\tunsigned long insn, rd;\n \tint shift = 0, len = 0, insn_len = 0;\n \tstruct kvm_cpu_trap utrap = { 0 };\n \tstruct kvm_cpu_context *ct = &vcpu->arch.guest_context;\n@@ -408,44 +408,47 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t}\n \n \t/* Decode length of MMIO and shift */\n-\tif ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {\n+\tif (riscv_insn_is_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn & INSN_MASK_LB) == INSN_MATCH_LB) {\n+\t\trd = riscv_insn_lw_extract_xd(insn);\n+\t} else if (riscv_insn_is_lb(insn)) {\n \t\tlen = 1;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn & INSN_MASK_LBU) == INSN_MATCH_LBU) {\n+\t\trd = riscv_insn_lb_extract_xd(insn);\n+\t} else if (riscv_insn_is_lbu(insn)) {\n \t\tlen = 1;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {\n+\t\trd = riscv_insn_lbu_extract_xd(insn);\n+\t} else if (riscv_insn_is_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {\n+\t\trd = riscv_insn_ld_extract_xd(insn);\n+\t} else if (riscv_insn_is_lwu(insn)) {\n \t\tlen = 4;\n-#endif\n-\t} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {\n+\t\trd = riscv_insn_lwu_extract_xd(insn);\n+\t} else if (riscv_insn_is_lh(insn)) {\n \t\tlen = 2;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {\n+\t\trd = riscv_insn_lh_extract_xd(insn);\n+\t} else if (riscv_insn_is_lhu(insn)) {\n \t\tlen = 2;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {\n+\t\trd = riscv_insn_lhu_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&\n-\t\t ((insn >> SH_RD) & 0x1f)) {\n+\t\trd = riscv_insn_c_ld_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_ldsp(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-#endif\n-\t} else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {\n+\t\trd = riscv_insn_c_ldsp_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(ulong) - len);\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&\n-\t\t ((insn >> SH_RD) & 0x1f)) {\n+\t\trd = riscv_insn_c_lw_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_lwsp(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(ulong) - len);\n+\t\trd = riscv_insn_c_lwsp_extract_xd(insn);\n \t} else {\n \t\treturn -EOPNOTSUPP;\n \t}\n@@ -455,7 +458,7 @@ int kvm_riscv_vcpu_mmio_load(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\treturn -EIO;\n \n \t/* Save instruction decode info */\n-\tvcpu->arch.mmio_decode.insn = insn;\n+\tvcpu->arch.mmio_decode.rd = rd;\n \tvcpu->arch.mmio_decode.insn_len = insn_len;\n \tvcpu->arch.mmio_decode.shift = shift;\n \tvcpu->arch.mmio_decode.len = len;\n@@ -498,11 +501,7 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\t\t unsigned long fault_addr,\n \t\t\t unsigned long htinst)\n {\n-\tu8 data8;\n-\tu16 data16;\n-\tu32 data32;\n-\tu64 data64;\n-\tulong data;\n+\tulong data, rs2;\n \tunsigned long insn;\n \tint len = 0, insn_len = 0;\n \tstruct kvm_cpu_trap utrap = { 0 };\n@@ -534,35 +533,30 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \t\tinsn_len = INSN_LEN(insn);\n \t}\n \n-\tdata = GET_RS2(insn, &vcpu->arch.guest_context);\n-\tdata8 = data16 = data32 = data64 = data;\n-\n-\tif ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {\n+\tif (riscv_insn_is_sw(insn)) {\n \t\tlen = 4;\n-\t} else if ((insn & INSN_MASK_SB) == INSN_MATCH_SB) {\n+\t\trs2 = riscv_insn_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sb(insn)) {\n \t\tlen = 1;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {\n+\t\trs2 = riscv_insn_sb_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sd(insn)) {\n \t\tlen = 8;\n-#endif\n-\t} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {\n+\t\trs2 = riscv_insn_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sh(insn)) {\n \t\tlen = 2;\n-#ifdef CONFIG_64BIT\n-\t} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {\n+\t\trs2 = riscv_insn_sh_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sd(insn)) {\n \t\tlen = 8;\n-\t\tdata64 = GET_RS2S(insn, &vcpu->arch.guest_context);\n-\t} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP &&\n-\t\t ((insn >> SH_RD) & 0x1f)) {\n+\t\trs2 = riscv_insn_c_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sdsp(insn)) {\n \t\tlen = 8;\n-\t\tdata64 = GET_RS2C(insn, &vcpu->arch.guest_context);\n-#endif\n-\t} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {\n+\t\trs2 = riscv_insn_c_sdsp_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sw(insn)) {\n \t\tlen = 4;\n-\t\tdata32 = GET_RS2S(insn, &vcpu->arch.guest_context);\n-\t} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP &&\n-\t\t ((insn >> SH_RD) & 0x1f)) {\n+\t\trs2 = riscv_insn_c_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_swsp(insn)) {\n \t\tlen = 4;\n-\t\tdata32 = GET_RS2C(insn, &vcpu->arch.guest_context);\n+\t\trs2 = riscv_insn_c_swsp_extract_xs2(insn);\n \t} else {\n \t\treturn -EOPNOTSUPP;\n \t}\n@@ -571,26 +565,24 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n \tif (fault_addr & (len - 1))\n \t\treturn -EIO;\n \n-\t/* Save instruction decode info */\n-\tvcpu->arch.mmio_decode.insn = insn;\n \tvcpu->arch.mmio_decode.insn_len = insn_len;\n-\tvcpu->arch.mmio_decode.shift = 0;\n-\tvcpu->arch.mmio_decode.len = len;\n \tvcpu->arch.mmio_decode.return_handled = 0;\n \n+\tdata = *((ulong *)(&vcpu->arch.guest_context) + rs2);\n+\n \t/* Copy data to kvm_run instance */\n \tswitch (len) {\n \tcase 1:\n-\t\t*((u8 *)run->mmio.data) = data8;\n+\t\t*((u8 *)run->mmio.data) = data;\n \t\tbreak;\n \tcase 2:\n-\t\t*((u16 *)run->mmio.data) = data16;\n+\t\t*((u16 *)run->mmio.data) = data;\n \t\tbreak;\n \tcase 4:\n-\t\t*((u32 *)run->mmio.data) = data32;\n+\t\t*((u32 *)run->mmio.data) = data;\n \t\tbreak;\n \tcase 8:\n-\t\t*((u64 *)run->mmio.data) = data64;\n+\t\t*((u64 *)run->mmio.data) = data;\n \t\tbreak;\n \tdefault:\n \t\treturn -EOPNOTSUPP;\n@@ -626,18 +618,13 @@ int kvm_riscv_vcpu_mmio_store(struct kvm_vcpu *vcpu, struct kvm_run *run,\n */\n int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)\n {\n-\tu8 data8;\n-\tu16 data16;\n-\tu32 data32;\n-\tu64 data64;\n-\tulong insn;\n \tint len, shift;\n+\tunsigned long data;\n \n \tif (vcpu->arch.mmio_decode.return_handled)\n \t\treturn 0;\n \n \tvcpu->arch.mmio_decode.return_handled = 1;\n-\tinsn = vcpu->arch.mmio_decode.insn;\n \n \tif (run->mmio.is_write)\n \t\tgoto done;\n@@ -647,29 +634,23 @@ int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)\n \n \tswitch (len) {\n \tcase 1:\n-\t\tdata8 = *((u8 *)run->mmio.data);\n-\t\tSET_RD(insn, &vcpu->arch.guest_context,\n-\t\t\t(long)data8 << shift >> shift);\n+\t\tdata = *((u8 *)run->mmio.data);\n \t\tbreak;\n \tcase 2:\n-\t\tdata16 = *((u16 *)run->mmio.data);\n-\t\tSET_RD(insn, &vcpu->arch.guest_context,\n-\t\t\t(long)data16 << shift >> shift);\n+\t\tdata = *((u16 *)run->mmio.data);\n \t\tbreak;\n \tcase 4:\n-\t\tdata32 = *((u32 *)run->mmio.data);\n-\t\tSET_RD(insn, &vcpu->arch.guest_context,\n-\t\t\t(long)data32 << shift >> shift);\n+\t\tdata = *((u32 *)run->mmio.data);\n \t\tbreak;\n \tcase 8:\n-\t\tdata64 = *((u64 *)run->mmio.data);\n-\t\tSET_RD(insn, &vcpu->arch.guest_context,\n-\t\t\t(long)data64 << shift >> shift);\n+\t\tdata = *((u64 *)run->mmio.data);\n \t\tbreak;\n \tdefault:\n \t\treturn -EOPNOTSUPP;\n \t}\n \n+\t*((ulong *)(&vcpu->arch.guest_context) + vcpu->arch.mmio_decode.rd) =\n+\t\t(long)data << shift >> shift;\n done:\n \t/* Move to next instruction */\n \tvcpu->arch.guest_context.sepc += vcpu->arch.mmio_decode.insn_len;\n","prefixes":["11/16"]}