{"id":2220718,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220718/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407195922.196410-17-pierrick.bouvier@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260407195922.196410-17-pierrick.bouvier@linaro.org>","date":"2026-04-07T19:59:17","name":"[v10,16/21] target/arm/tcg/translate-a64.c: use translator_ldl_end instead of arm_ldl_code","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9d04d37535c006cd91710b7d9ce569350d9368c7","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/1.1/people/85798/?format=json","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407195922.196410-17-pierrick.bouvier@linaro.org/mbox/","series":[{"id":499034,"url":"http://patchwork.ozlabs.org/api/1.1/series/499034/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499034","date":"2026-04-07T19:59:01","name":"target/arm: single-binary","version":10,"mbox":"http://patchwork.ozlabs.org/series/499034/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220718/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220718/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=avSdpgUK;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::1032;\n envelope-from=pierrick.bouvier@linaro.org; helo=mail-pj1-x1032.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Allows to reduce scope of target/arm/tcg/arm_ldst.h to aarch32 only.\n\nSuggested-by: Richard Henderson \nReviewed-by: Richard Henderson \nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: Pierrick Bouvier \n---\n target/arm/tcg/translate-a64.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)","diff":"diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex df2cbd66b38..48b5c572555 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -26,7 +26,6 @@\n #include \"translate-a64.h\"\n #include \"tcg/tcg-op.h\"\n #include \"qemu/log.h\"\n-#include \"arm_ldst.h\"\n #include \"semihosting/semihost.h\"\n #include \"cpregs.h\"\n \n@@ -10801,7 +10800,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n if (pc & 3) {\n /*\n * PC alignment fault. This has priority over the instruction abort\n- * that we would receive from a translation fault via arm_ldl_code.\n+ * that we would receive from a translation fault via translator_ldl_end.\n * This should only be possible after an indirect branch, at the\n * start of the TB.\n */\n@@ -10813,7 +10812,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n }\n \n s->pc_curr = pc;\n- insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);\n+ /* Code is always little-endian on Aarch64 */\n+ insn = translator_ldl_end(env, &s->base, pc, MO_LE);\n s->insn = insn;\n s->base.pc_next = pc + 4;\n \n","prefixes":["v10","16/21"]}