{"id":2220688,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220688/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407141809.16862-14-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260407141809.16862-14-mohamed@unpredictable.fr>","date":"2026-04-07T14:18:09","name":"[v8,13/13] whpx: i386: interrupt priority support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ea91e5f0bee5c43c9a841c07a3f4bf2b8d0d61ed","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407141809.16862-14-mohamed@unpredictable.fr/mbox/","series":[{"id":499029,"url":"http://patchwork.ozlabs.org/api/1.1/series/499029/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499029","date":"2026-04-07T14:17:59","name":"whpx: i386: bug fixes, feature probing and CPUID","version":8,"mbox":"http://patchwork.ozlabs.org/series/499029/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220688/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220688/checks/","tags":{},"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=UM/3yrGI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=outbound.qs.icloud.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development <qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<https://lists.nongnu.org/archive/html/qemu-devel>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Implement APIC IRR interrupt priorities.\n\nEven with kernel-irqchip=off, Hyper-V is aware of interrupt priorities\nand implements CR8/TPR, with the InterruptPriority field being followed.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n target/i386/whpx/whpx-all.c | 27 +++++++++++++++++++++++----\n 1 file changed, 23 insertions(+), 4 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 7a31dc6427..569da3b90d 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -1588,6 +1588,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n     UINT32 reg_count = 0;\n     WHV_REGISTER_VALUE reg_values[3];\n     WHV_REGISTER_NAME reg_names[3];\n+    int irr = apic_get_highest_priority_irr(x86_cpu->apic_state);\n \n     memset(&new_int, 0, sizeof(new_int));\n     memset(reg_values, 0, sizeof(reg_values));\n@@ -1623,10 +1624,23 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n         }\n     }\n \n+    if (irr == -1) {\n+        if (!(!apic_accept_pic_intr(x86_cpu->apic_state) || !pic_get_output(isa_pic))) {\n+            /* In case it's a PIC interrupt not going through APIC */\n+            irr = 0;\n+        } else if (whpx_irqchip_in_kernel()) {\n+            /* if kernel-irqchip=on, APIC interrupts aren't injected here. */\n+            irr = 0;\n+        } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n+            abort();\n+        }\n+    }\n+\n     /* Get pending hard interruption or replay one that was overwritten */\n     if (!whpx_irqchip_in_kernel()) {\n         if (!vcpu->interruption_pending &&\n-            vcpu->interruptable && (env->eflags & IF_MASK)) {\n+            vcpu->interruptable && (env->eflags & IF_MASK)\n+            && (vcpu->tpr < irr || irr == 0)) {\n             assert(!new_int.InterruptionPending);\n             if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n                 cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);\n@@ -1683,13 +1697,17 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n     }\n \n     /* Update the state of the interrupt delivery notification */\n-    if (!vcpu->window_registered &&\n+    if ((!vcpu->window_registered ||\n+        (vcpu->window_priority < irr && vcpu->window_priority != 0) ||\n+        (irr == 0 && vcpu->window_priority != 0)) &&\n         cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) {\n         reg_values[reg_count].DeliverabilityNotifications =\n             (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) {\n-                .InterruptNotification = 1\n+                .InterruptNotification = 1,\n+                .InterruptPriority = irr >> 4\n             };\n         vcpu->window_registered = 1;\n+        vcpu->window_priority = irr;\n         reg_names[reg_count] = WHvX64RegisterDeliverabilityNotifications;\n         reg_count += 1;\n     }\n@@ -1703,7 +1721,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n             reg_names, reg_count, reg_values);\n         if (FAILED(hr)) {\n             error_report(\"WHPX: Failed to set interrupt state registers,\"\n-                         \" hr=%08lx\", hr);\n+                         \" hr=%08lx, InterruptPriority=%i\", hr, irr >> 4);\n         }\n     }\n }\n@@ -1919,6 +1937,7 @@ int whpx_vcpu_run(CPUState *cpu)\n         case WHvRunVpExitReasonX64InterruptWindow:\n             vcpu->ready_for_pic_interrupt = 1;\n             vcpu->window_registered = 0;\n+            vcpu->window_priority = 0;\n             ret = 0;\n             break;\n \n","prefixes":["v8","13/13"]}