{"id":2220526,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220526/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-d3cold-v4-4-bb171f75b465@oss.qualcomm.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260407-d3cold-v4-4-bb171f75b465@oss.qualcomm.com>","date":"2026-04-07T13:03:11","name":"[v4,4/5] PCI: dwc: Use common D3cold eligibility helper in suspend path","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2fd08826fe6562f34ec08f28ac5f1139ab3d68b3","submitter":{"id":89908,"url":"http://patchwork.ozlabs.org/api/1.1/people/89908/?format=json","name":"Krishna Chaitanya Chundru","email":"krishna.chundru@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-d3cold-v4-4-bb171f75b465@oss.qualcomm.com/mbox/","series":[{"id":498980,"url":"http://patchwork.ozlabs.org/api/1.1/series/498980/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498980","date":"2026-04-07T13:03:07","name":"PCI: qcom: Add D3cold support","version":4,"mbox":"http://patchwork.ozlabs.org/series/498980/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220526/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220526/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=ZiIApgK/;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=V+kDmxQz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52063-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"ZiIApgK/\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"V+kDmxQz\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.168.131","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com"],"Received":["from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqmfS2kLfz1xy1\n\tfor ; Tue, 07 Apr 2026 23:06:08 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 2C9E1306AA50\n\tfor ; Tue, 7 Apr 2026 13:03:55 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 040923B3884;\n\tTue, 7 Apr 2026 13:03:46 +0000 (UTC)","from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B1983B7753\n\tfor ; Tue, 7 Apr 2026 13:03:44 +0000 (UTC)","from pps.filterd (m0279866.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6376Ym6l494121\n\tfor ; Tue, 7 Apr 2026 13:03:44 GMT","from mail-pl1-f198.google.com (mail-pl1-f198.google.com\n [209.85.214.198])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dcmr8trnm-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor ; Tue, 07 Apr 2026 13:03:43 +0000 (GMT)","by mail-pl1-f198.google.com with SMTP id\n d9443c01a7336-2b0cac007cdso34961835ad.3\n for ; Tue, 07 Apr 2026 06:03:43 -0700 (PDT)","from hu-krichai-hyd.qualcomm.com ([202.46.23.25])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b2749794e8sm181564885ad.53.2026.04.07.06.03.34\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 07 Apr 2026 06:03:38 -0700 (PDT)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775567025; cv=none;\n b=F8+wWAi+O1IwF2Rc+/mFTxYD9l6+iq/A/koS9iHAh6iVPpr0wOOosD/0VTu/sa3yA4Z4cqiidF7FF49qYOEWVJVKrGVcc1qQoELxqSJv0QC5TQBewSiSknhGjYpOr2zDxc8/frETLC9/U/Ol9piZTX3nDofQ+Zufth+UvMowxvI=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775567025; c=relaxed/simple;\n\tbh=PWGUXyr+GtnyzoUhMB9V3ekI1oFO0F8QmYYXumVt7Kw=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=TBt3OagZBNOgh/9Si4J9cb4QokNkJUpL9FcX6bQ+PU2GO0e8iV8Sfv3qwd0Gaeksbrm0Eg4536NxPm0vUym9539720awyc024YKfW6aPiptm+3XBl4eAsJzoGTcyT9hCWlbjoqDZ2rNdUBrcHUoss7KptF2xDJI1On4Sw4/TkVY=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com;\n spf=pass smtp.mailfrom=oss.qualcomm.com;\n dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=ZiIApgK/;\n dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=V+kDmxQz; arc=none smtp.client-ip=205.220.168.131","DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to; s=qcppdkim1; bh=\n\t7aQXCO2yyCZ+oTPzSKSvjrummEe0+JiJFnwfrGu6ciE=; b=ZiIApgK/+yc6CkXF\n\tzTDxjb5yYtlLxm2mIu3jnHCnxW1Wf7FV8XXSykWVv1VrOcNgsuUOvt8SRdL1PD+k\n\tVTlc4TwID0X4zeboZ55PX7JSygwvRMnzYL+2mo096F2JcFPsoqHF1MIkRxfCOzVQ\n\tU71PaiBwMVtbzgLLB/M/sGpLSnoC5/api0/wudeOCCivarkAByAFamJaX6xosVlx\n\tctsl7axMgQtM/z/Jsboi4VO1/4pbnsMrSuDDbMlJR9ytKugAC8B1ytE6npAfnJyS\n\tlGvVEUSWUfoAG9LcgzWfxNihGPAPb3BaA1+NJjivyb14ddzK8ah5SjDGA1hcbSbs\n\tG8VPGQ==","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775567023; x=1776171823;\n darn=vger.kernel.org;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to;\n bh=7aQXCO2yyCZ+oTPzSKSvjrummEe0+JiJFnwfrGu6ciE=;\n b=V+kDmxQzYNSsksM8qiAOA14erOBvDWy0d0WWD4BJkRBAcM9EuDKmv9r96+Qa6NcOlN\n KJOwX9JE1Jufa+y+vHk5O5brQ/pZGlq5RnqkPHAY3CVIE0hFlwaNxESqJuziOgLdEP+P\n 0XHXGlIRXriRG2IKzQjl2PzzpiPMp2yfOUD8aBYRX+L2j0OwUEQvBdRwe5byn9Gt4oLt\n /e7rX2IinQp8WleXA0WYJLtLS7NMMpfu6AdPx1AAAwqQ+izVNtHW9GMZpZ/nWpm4K7pr\n iCqisSV7J13wrmaIBfV/FJfwUeRekNg+JpDZs8bid1UJkPYsDCx4glSXGVkNtP5SPaqv\n 8oHQ=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775567023; x=1776171823;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=7aQXCO2yyCZ+oTPzSKSvjrummEe0+JiJFnwfrGu6ciE=;\n b=nz+Zd4kfor8xVCd1r1Q3Y1xhg++n+OqR3sHjpa6/+fhXQtIOwEqaDVzle/ULBnHUqb\n MH/XHKkkNJh9YlBpmNt0QQBgaj07rlz8O/NSYHKS45hwL7cQU2GbRhKStOpfOrGL6IfF\n YpOfDarSKMAHygDMNIXmuyzSAuCUZx5DpReaKsB60S0OdjUea16jCe2Jn9Hzlf4EkGQb\n W2dXTp4oiNTld+JOralFxnWi48XfwOWHZWQjI2IMssEsIlTGAI5DKETCAx7NN9tpOUrZ\n zJCOPRqKmm2Z1BcBnPj3x8o3qne6dTC2Uyh+0n8xC4e04iF0JZLXvWf4oBla2EgDYu0G\n TAZQ==","X-Gm-Message-State":"AOJu0YzeePKhbp1gNYlfGBnUTlf6YbNbit4qcScL+fsPvmjip+P7Y3TI\n\tH3fQmSpDp/SHnnyxo2ztc9WkETVFQj4VGX8htNWvGqldrCgsaPCmkpn8agxBAByVXpw4QxQGBwK\n\tyEnn65fSCP9gzbzgXpjii/71JRX1rTuJ354bqfThNKtHmmVcy/BvEW0teNxrTZgs=","X-Gm-Gg":"AeBDievPw/4g5Bf63bTPWh+Xgqx56m40toOx9vUM/SWbhqCGImkG5Qd+cKX9owwWE/j\n\tyIQ//mHDRzM6+d1imvpj/Rvjdyr7+uBSn/eDWkZdQSLdqBIH5Ou8vbtlZYV25LLuYohM6KHqJVu\n\tMRMoXdNyxfuCcu6BgSRIB2M3XITqWNlum215TWqVdKQEWFPIEk1PSL2BVVEdg3J7AUhcTOLgjN6\n\tHYXxh7swMkP2H9gjRHhMNOYHFtMHE/0X9nBRB5zLW/w5PQ2hUnetbqHHQ198aGMVJTAIf9aJ7Co\n\t90nrDpnrj8KjKJw8gITkWlNEe4DpkfFMSe4IXOKLuho/+T9Imfn7XoyZtOyDNe8XYOHNP4n7Jgr\n\tUJr1+BJL2Tbctv08hk0K73JrE3QlS6p9S+fyf+q0MPwu/e2fnfbZ6GfDq","X-Received":["by 2002:a17:902:c410:b0:2b2:4862:78e9 with SMTP id\n d9443c01a7336-2b281687c7fmr191332725ad.15.1775567023092;\n Tue, 07 Apr 2026 06:03:43 -0700 (PDT)","by 2002:a17:902:c410:b0:2b2:4862:78e9 with SMTP id\n d9443c01a7336-2b281687c7fmr191332045ad.15.1775567022518;\n Tue, 07 Apr 2026 06:03:42 -0700 (PDT)"],"From":"Krishna Chaitanya Chundru ","Date":"Tue, 07 Apr 2026 18:33:11 +0530","Subject":"[PATCH v4 4/5] PCI: dwc: Use common D3cold eligibility helper in\n suspend path","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260407-d3cold-v4-4-bb171f75b465@oss.qualcomm.com>","References":"<20260407-d3cold-v4-0-bb171f75b465@oss.qualcomm.com>","In-Reply-To":"<20260407-d3cold-v4-0-bb171f75b465@oss.qualcomm.com>","To":"Jingoo Han ,\n Manivannan Sadhasivam ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= , Rob Herring ,\n Bjorn Helgaas , Will Deacon ","Cc":"linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru ","X-Mailer":"b4 0.14.2","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775566995; l=3264;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=PWGUXyr+GtnyzoUhMB9V3ekI1oFO0F8QmYYXumVt7Kw=;\n b=SYyzydNs/xfRblTu6iPrQSA4fMH41W/iB9N/GrQWpymTxH13o3VAyw2wznzKk6+5Owe6OlR3I\n qZTMEZWhJEqDsdL6LeSIjDaj91CGvrIy8scrP0kmGcdSnWG7Whu2/lL","X-Developer-Key":"i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=","X-Proofpoint-GUID":"dKJbK4D4tlYIHNy0f-gfhMCgX_zY44Hp","X-Proofpoint-ORIG-GUID":"dKJbK4D4tlYIHNy0f-gfhMCgX_zY44Hp","X-Authority-Analysis":"v=2.4 cv=c9abhx9l c=1 sm=1 tr=0 ts=69d500af cx=c_pps\n a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22\n a=EUspDBNiAAAA:8 a=h5qRVDGUHOPEFS6InpEA:9 a=QEXdDO2ut3YA:10\n a=GvdueXVYPmCkWapjIL-Q:22","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA3MDEyMSBTYWx0ZWRfX8U5gBvL724fw\n KravXWcaVtpRE01mXexudEeLhUXwBUXh1GYHNHRGK2dEivR+ZbN8Aab+cXxWCViOgo3E7iw0b7l\n 1S328St4g8aEcPIcVtmGtkngyeUWhQd8Ln42lPd9MrFDZf7QfxlCyEeYfxLMDfBehH/tyl0iq+2\n WE1noD2WEHVeD9w+MEvecFq277moHLBEGV55P3BnCn6Ko6JQ9NFiDVaUOgwbDqX2GrEHeKjsnRj\n H/ShwVfODOHxenDBevwiHC0aAmJ3LEwZsAzwQdTwSoAaR0sIleykYzJUcTMVnmmGLIW8tTo3a4f\n pD60JZHvDe+W0Zbia3eJScC9RarPHfwjebDh2No8PhZJ77IPUA7nbjqYGipsCFiXd6iwyJ4HAs9\n nCLmHyDOg5R9l3+iX29hXDGxTKOxLHEtwfN18tl2uWFxfymr4tL/1Wn+tZNBI+JSHiPp9Me4RwO\n n0FkaemAF0vd3DO2bTg==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-07_02,2026-04-07_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501\n bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070121"},"content":"Previously, the driver skipped putting the link into L2/device state in\nD3cold whenever L1 ASPM was enabled, since some devices (e.g. NVMe) expect\nlow resume latency and may not tolerate deeper power states. However, such\ndevices typically remain in D0 and are already covered by the new helper's\nrequirement that all endpoints be in D3hot before the devices under host\nbridge may enter D3cold.\n\nSo, replace the local L1/L1SS-based check in dw_pcie_suspend_noirq() with\nthe shared pci_host_common_d3cold_possible() helper to decide whether the\ndevices under host bridge can safely transition to D3cold.\n\nIn addition, propagate PME-from-D3cold capability information from the\nhelper and record it in skip_pwrctrl_off. Some devices (e.g. M.2 cards\nwithout auxiliary power) may lose PME detection when main power is\nremoved, even if they advertise PME-from-D3cold support. This allows\ncontroller power-off to be skipped when required to preserve wakeup\nfunctionality.\n\nSigned-off-by: Krishna Chaitanya Chundru \n---\n drivers/pci/controller/dwc/pcie-designware-host.c | 11 +++++------\n drivers/pci/controller/dwc/pcie-designware.h | 1 +\n 2 files changed, 6 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c\nindex 6ae6189e9b8a9021c99ece17504834650debd86b..ce3093cfd1608f1616001cbf5f541a4dc3eafea5 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-host.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-host.c\n@@ -16,9 +16,11 @@\n #include \n #include \n #include \n+#include \n #include \n #include \n \n+#include \"../pci-host-common.h\"\n #include \"../../pci.h\"\n #include \"pcie-designware.h\"\n \n@@ -1218,18 +1220,14 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)\n \n int dw_pcie_suspend_noirq(struct dw_pcie *pci)\n {\n-\tu8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n+\tbool pme_capable = false;\n \tint ret = 0;\n \tu32 val;\n \n \tif (!dw_pcie_link_up(pci))\n \t\tgoto stop_link;\n \n-\t/*\n-\t * If L1SS is supported, then do not put the link into L2 as some\n-\t * devices such as NVMe expect low resume latency.\n-\t */\n-\tif (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)\n+\tif (!pci_host_common_d3cold_possible(pci->pp.bridge, &pme_capable))\n \t\treturn 0;\n \n \tif (pci->pp.ops->pme_turn_off) {\n@@ -1269,6 +1267,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)\n \tudelay(1);\n \n stop_link:\n+\tpci->pp.skip_pwrctrl_off = pme_capable;\n \tdw_pcie_stop_link(pci);\n \tif (pci->pp.ops->deinit)\n \t\tpci->pp.ops->deinit(&pci->pp);\ndiff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h\nindex ae6389dd9caa5c27690f998d58729130ea863984..0af083018aee29c1f0f4385dacc6e878c8d040de 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.h\n+++ b/drivers/pci/controller/dwc/pcie-designware.h\n@@ -447,6 +447,7 @@ struct dw_pcie_rp {\n \tbool\t\t\tecam_enabled;\n \tbool\t\t\tnative_ecam;\n \tbool skip_l23_ready;\n+\tbool\t\t\tskip_pwrctrl_off;\n };\n \n struct dw_pcie_ep_ops {\n","prefixes":["v4","4/5"]}