{"id":2220524,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220524/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-d3cold-v4-3-bb171f75b465@oss.qualcomm.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260407-d3cold-v4-3-bb171f75b465@oss.qualcomm.com>","date":"2026-04-07T13:03:10","name":"[v4,3/5] PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d807b402a2f216f9552173ee8cd0ed554b6daae9","submitter":{"id":89908,"url":"http://patchwork.ozlabs.org/api/1.1/people/89908/?format=json","name":"Krishna Chaitanya Chundru","email":"krishna.chundru@oss.qualcomm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-d3cold-v4-3-bb171f75b465@oss.qualcomm.com/mbox/","series":[{"id":498980,"url":"http://patchwork.ozlabs.org/api/1.1/series/498980/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498980","date":"2026-04-07T13:03:07","name":"PCI: qcom: Add D3cold support","version":4,"mbox":"http://patchwork.ozlabs.org/series/498980/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220524/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220524/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=neYlXzff;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Pr2vuRZs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; 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a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=","X-Authority-Analysis":"v=2.4 cv=OKEXGyaB c=1 sm=1 tr=0 ts=69d500a8 cx=c_pps\n a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22\n a=EUspDBNiAAAA:8 a=S-wDCh2AgS0RhsWIeBgA:9 a=QEXdDO2ut3YA:10\n a=mQ_c8vxmzFEMiUWkPHU9:22","X-Proofpoint-GUID":"rwc_btRyMMRMXFtXiPAMBTFD9g_dgvqG","X-Proofpoint-ORIG-GUID":"rwc_btRyMMRMXFtXiPAMBTFD9g_dgvqG","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDA3MDEyMSBTYWx0ZWRfXx9SisgwxOF7Q\n w2aDG19vd/gBWELEuuRaJ+ANs6ywZKQNJR9qBwuyIIl4PNvA+ZFwMXO1LJW7QgjsyvN+gsjdUPb\n 4ekcbJIE/YLICocBjHSO1noCBEg9Wf+xn7J/QjSQkutG8GI9b3xBQNV5RySL4T7hZozRfXBLGQd\n D0e0drCvLciGg8OeyFJ/xYFr2gr4Zrv4+3mM9ipjngWTLfXtNIvXpB1VZ/OZToZFKS1TQv3z01R\n eXAR9GAkqJb2hEaGbGJFz+bTnrjt2ZmiKEDxQXKN8y9Y3gm86g8p+wq0jrgHpsOcilfLExhC7xC\n Ph91Ti3IViXttf2Kbgby9rlGrXZWgc3+Hi2rQ2xM7n0kD0A/0yTZMLJwO3hNSAdXCuqa4kb+y/1\n BU4OxWCso1MFnZBcFzGYJiKTRfdocWJ9Nd+e1EoFHxsGkVuBIGhiwZx22dE431MYirutrCweuCG\n ICSGk7YsKe2AD9vDlwQ==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-07_02,2026-04-07_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n bulkscore=0 priorityscore=1501 spamscore=0 impostorscore=0 lowpriorityscore=0\n clxscore=1015 adultscore=0 malwarescore=0 suspectscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070121"},"content":"Some Qcom PCIe controller variants bring the PHY out of test power-down\n(PHY_TEST_PWR_DOWN) during init. When the link is later transitioned\ntowards D3cold and the driver disables PCIe clocks and/or regulators\nwithout explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain\npartially powered, leading to avoidable power leakage.\n\nUpdate the init-path comments to reflect that PARF_PHY_CTRL is used to\npower the PHY on. Also, for controller revisions that enable PHY power\nin init (2.3.2, 2.3.3, 2.7.0 and 2.9.0), explicitly power the PHY down\nvia PARF_PHY_CTRL in the deinit path before disabling clocks/regulators.\n\nThis ensures the PHY is put into a defined low-power state prior to\nremoving its supplies, preventing leakage when entering D3cold.\n\nSigned-off-by: Krishna Chaitanya Chundru \n---\n drivers/pci/controller/dwc/pcie-qcom.c | 32 +++++++++++++++++++++++++++++---\n 1 file changed, 29 insertions(+), 3 deletions(-)","diff":"diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex b00bf46637a5ff803a845719c5b0b5b82739244b..c14c3eb70f356b6ad8a2ffe48b107327d2babf77 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -513,7 +513,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)\n \tu32 val;\n \tint ret;\n \n-\t/* enable PCIe clocks and resets */\n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -680,6 +680,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state*/\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n \tregulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);\n@@ -712,7 +718,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)\n {\n \tu32 val;\n \n-\t/* enable PCIe clocks and resets */\n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -844,6 +850,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n }\n@@ -899,6 +911,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)\n \tu16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tu32 val;\n \n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -994,7 +1007,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)\n \t/* configure PCIe to RC mode */\n \twritel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);\n \n-\t/* enable PCIe clocks and resets */\n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -1065,6 +1078,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n \n@@ -1169,6 +1188,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n }\n@@ -1209,6 +1234,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)\n \tu32 val;\n \tint i;\n \n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n","prefixes":["v4","3/5"]}