{"id":2220464,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220464/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407104154.2842132-2-sherry.sun@nxp.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260407104154.2842132-2-sherry.sun@nxp.com>","date":"2026-04-07T10:41:43","name":"[V11,01/12] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in Root Port node","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"3251068ee9e53f63b745075ba6ef7f82383237bb","submitter":{"id":77063,"url":"http://patchwork.ozlabs.org/api/1.1/people/77063/?format=json","name":"Sherry Sun","email":"sherry.sun@nxp.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407104154.2842132-2-sherry.sun@nxp.com/mbox/","series":[{"id":498961,"url":"http://patchwork.ozlabs.org/api/1.1/series/498961/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498961","date":"2026-04-07T10:41:47","name":"pci-imx6: Add support for parsing the reset property in new Root Port binding","version":11,"mbox":"http://patchwork.ozlabs.org/series/498961/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220464/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220464/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=nxp.com header.i=@nxp.com header.a=rsa-sha256\n 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","To":"robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de","Cc":"imx@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH V11 01/12] dt-bindings: PCI: fsl,imx6q-pcie: Add reset GPIO in\n Root Port node","Date":"Tue, 7 Apr 2026 18:41:43 +0800","Message-Id":"<20260407104154.2842132-2-sherry.sun@nxp.com>","X-Mailer":"git-send-email 2.37.1","In-Reply-To":"<20260407104154.2842132-1-sherry.sun@nxp.com>","References":"<20260407104154.2842132-1-sherry.sun@nxp.com>","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-ClientProxiedBy":"MA5P287CA0060.INDP287.PROD.OUTLOOK.COM\n (2603:1096:a01:1d3::9) To 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X0VpHHrVh/JKsNCtr1ou2q7OLwAWclYFZ+V7NuPPcUzG07RFK5yEtv2H0o1oJ2oaWMQ4ETnFLWkFSuT4PmDs/PNncQMl10Wsb5pDbWekwV+Kiq77u56HWY2tRPU3jQ7wG+GlykpGWoM9B7XwPPOO4ZmSzubLk2Wv+wNTsLscHheoIqUBfnBlYKNfXPEQh4JMWa5fNx33BxfntUm1IKQJV4XULN9uyLlHaCrzy4OvDiLaAaCzSEVAl1rcGRwQjFfTDTS2QSkz/HBJzt+fF2D/+h41QZS5QNQ+ZiXb8rKnk2RqbpvJL/kskmMSWvFMWlMqqKsKOmgYqgPKDGe/u0Ylc2z1a92CjaGsYmyIDDssGF1A3FjhWJCfuoixKPZ9JvRGciL/LztKTJSD65NIJAymaadkLE0kW07Vw8fcZ8wooo/yh3qXkK1UIdn1skIGoSEpqnaNGwCZ6qoH/JboG/9Z3Owd/zXAY00rqvu3fcaLmTxPQp77dcPhilNRL/2TcuFEIQQ8X0gEGjws858vhlI87aqH1M9vf5PxOJaBBXJn+0dyg50ik0qxv41vGaxteug74p6ZzvA5WcNRybCSKm7NSAqEN6KiXcRn9bWf4tVjnDGQVUJo+ZZ6EsGu1AyfvC45xkgGciovQJmbx3qczqkZP70Z2hsh+ts1rUloeZBZKyoSXXAa9N+aAOxBNYVDzrrHDAFvPs/PGuO3XR6+/Y07ccW1CyBeVqmRVnN7XINz8pWHp9+DeTfCBOavKM8QB1p7ujJ1/CFEx52/QHBfn8olnfdyaJinR6CgHEj/7YtcBdkMDOSTxz+n2yWPTJFTrP9TQ+fXOIAR2FJ2TjMsuFQmLA7043XGW5x9M2EFI1yGs6OrQIWvs6/lyblglJ0FU9kYmzTkq9EnMQuSsEsve/LcnJKAiAd3eOKMc4FpQUT1y01FEpq296nIu6KgCTRiX65VyJsZQbik8tMYFpsz9Y33GtAklaJf9t66Wpg7mih4gM8/0M+wQa+VrN22lYkWwO8/+FoyaV5YyQcT39a+WKmpshjbk76e+ytSKQjl2UIyYTkQI3w0lruhnpB0on8px5hJjTM5gf648A2WU6O2iAg+DNzmlJO1rrzFqmXz9iA1mXXx96UrihCpGqhdU4kG4L1Ad301ezondqvOg80PMS2W0w78/cSDbMuBVOe51l9URCCYHzMw3PFwjTjzgEEk3reO6Nv83NNmybIqO/XtrG/k6Ob4vKTYnyojB7QWNPBevsmQhey7QJ9KZp6pR+6fEQHkH/XImgf6HULMkwFBzib3VslikFWfw2M4f8sZ3mPFc0JD9syTZFPar/BPhDXqLlsu/gNGNmFhGeGuxhaF7y4785GsdwllYuMDKeAB008fMeTiNq29/1Hf6purnhb1xDGNYpf93j1/KDelsBEXddirBs62jj3gfmdqjcKvKj+j14/PsyyK8wFzpiilXOlbWr2cZsfwrhdK6CvWig/gcITGv1JS4HZVTvi1mr84zcdGaFuptqWg2KWKG6VD86Y+Z3LZcSRpvRLInufhAJvWJ2EIUeLswEvnrkzB3H4PhKpWERSSXmPAw9KpyIWjRHJ6Xjs9LOMZxiKOtmpnIJHY0yIvy+pEeRIY8+rAoeilruVNQUcy4Ke2wZ2zjqTI6fvTOPVSNW6Le6dxqC4VXdEZUPNIMUgb9kUSFknrn4YwFKQ6ouC23sIoJt6aDKHIkvVYbtUbfkK9VxLzfdg7SgWs0x0ZHA==","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 44fd92cb-dd48-4ed3-8b28-08de9492469b","X-MS-Exchange-CrossTenant-AuthSource":"VI0PR04MB12114.eurprd04.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Internal","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"07 Apr 2026 10:41:50.4750\n (UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-CrossTenant-Id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-CrossTenant-MailboxType":"HOSTED","X-MS-Exchange-CrossTenant-UserPrincipalName":"\n Bq7IQkg49/tVYvnc86EEvGHn/rjns7pDjMp0lpCM8O0IwDZRgQ+83KndhKqppTQW3YPNP1CxqRezT3x7/UV5/A==","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"DB9PR04MB8281"},"content":"Update fsl,imx6q-pcie.yaml to include the standard reset-gpios property\nfor the Root Port node.\n\nThe reset-gpios property is already defined in pci-bus-common.yaml for\nPERST#, so use it instead of the local reset-gpio property. Keep the\nexisting reset-gpio property in the bridge node for backward\ncompatibility, but mark it as deprecated.\n\nSigned-off-by: Sherry Sun \nReviewed-by: Rob Herring (Arm) \n---\n .../bindings/pci/fsl,imx6q-pcie.yaml | 32 +++++++++++++++++++\n 1 file changed, 32 insertions(+)","diff":"diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\nindex 12a01f7a5744..d1a2526f43dc 100644\n--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml\n@@ -59,16 +59,34 @@ properties:\n - const: dma\n \n reset-gpio:\n+ deprecated: true\n description: Should specify the GPIO for controlling the PCI bus device\n reset signal. It's not polarity aware and defaults to active-low reset\n sequence (L=reset state, H=operation state) (optional required).\n+ This property is deprecated, instead of referencing this property from the\n+ host bridge node, use the reset-gpios property from the root port node.\n \n reset-gpio-active-high:\n+ deprecated: true\n description: If present then the reset sequence using the GPIO\n specified in the \"reset-gpio\" property is reversed (H=reset state,\n L=operation state) (optional required).\n+ This property is deprecated along with the reset-gpio property above, use\n+ the reset-gpios property from the root port node.\n type: boolean\n \n+ pcie@0:\n+ description:\n+ Describe the i.MX6 PCIe Root Port.\n+ type: object\n+ $ref: /schemas/pci/pci-pci-bridge.yaml#\n+\n+ properties:\n+ reg:\n+ maxItems: 1\n+\n+ unevaluatedProperties: false\n+\n required:\n - compatible\n - reg\n@@ -229,6 +247,7 @@ unevaluatedProperties: false\n examples:\n - |\n #include \n+ #include \n #include \n \n pcie: pcie@1ffc000 {\n@@ -255,5 +274,18 @@ examples:\n <&clks IMX6QDL_CLK_LVDS1_GATE>,\n <&clks IMX6QDL_CLK_PCIE_REF_125M>;\n clock-names = \"pcie\", \"pcie_bus\", \"pcie_phy\";\n+\n+ pcie_port0: pcie@0 {\n+ compatible = \"pciclass,0604\";\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;\n+ };\n };\n ...\n","prefixes":["V11","01/12"]}