{"id":2220366,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220366/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com/","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.1/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com>","date":"2026-04-07T02:40:52","name":"[v2,1/4] riscv: add UltraRISC SoC family Kconfig support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"14f995471df57b656e2ecb19d9530cfa64841730","submitter":{"id":92886,"url":"http://patchwork.ozlabs.org/api/1.1/people/92886/?format=json","name":"Jia Wang","email":"wangjia@ultrarisc.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com/mbox/","series":[{"id":498910,"url":"http://patchwork.ozlabs.org/api/1.1/series/498910/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pci/list/?series=498910","date":"2026-04-07T02:40:55","name":"riscv: Add PCIe support for UltraRISC DP1000 SoC","version":2,"mbox":"http://patchwork.ozlabs.org/series/498910/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220366/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220366/checks/","tags":{},"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ultrarisc.com header.i=@ultrarisc.com\n header.a=rsa-sha256 header.s=dkim header.b=TA1e7L70;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"<20260407-ultrarisc-pcie-v2-1-2aa2a19a7fb3@ultrarisc.com>","References":"<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>","In-Reply-To":"<20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com>","To":"Paul Walmsley , Palmer Dabbelt ,\n Albert Ou , Alexandre Ghiti ,\n Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= ,\n Manivannan Sadhasivam , Rob Herring ,\n Bjorn Helgaas , Jingoo Han ,\n Xincheng Zhang ,\n Krzysztof Kozlowski ,\n Conor Dooley ","Cc":"linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n Jia Wang ","X-Mailer":"b4 0.15-dev","X-Developer-Signature":"v=1; a=ed25519-sha256; t=1775529665; l=924;\n i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id;\n bh=P4GjG77njFnhJKKg9A7TX9zCDvXFIHaSQNO7h4lqj9E=;\n b=qbn5R6x4HJ8lCpXBgSbCqIU+8E7QUq5mB8cvupA3fI4AFYPa3fOMLgNxZdcftfBX2kGVzsjWh\n c3Bp9M21LRtDbXla88kbnP98xT1D0Xc/mwXRA/JzM0hWfkj/qIxdoWE","X-Developer-Key":"i=wangjia@ultrarisc.com; a=ed25519;\n pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U=","X-CM-TRANSID":"AQAAfwDXEELwbtRpBZsBAA--.862S3","X-Coremail-Antispam":"1UD129KBjvdXoW7Jw45Gr4DJry7tw1Utry8uFg_yoWfAwb_C3\n\ts7J3y8ua48AFW8ua98Wr4fWFyrCws8WFy3Gr1SqryUua4xXr17Xw4Dt3W8tr15uw15Xa1k\n\tZrZ3JFWfurySyjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT\n\t9fnUUIcSsGvfJTRUUUb9kFF20E14v26rWj6s0DM7CY07I20VC2zVCF04k26cxKx2IYs7xG\n\t6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUGwA2048vs2IY02\n\t0Ec7CjxVAFwI0_Gr0_Xr1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv\n\twVC0I7IYx2IY67AKxVWUJVWUCwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4\n\tx0Y4vEx4A2jsIE14v26r1j6r4UM28EF7xvwVC2z280aVCY1x0267AKxVW8JVW8Jr1le2I2\n\t62IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcV\n\tAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG\n\t0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI\n\t1lc7CjxVAaw2AFwI0_GFv_Wrylc2xSY4AK6svPMxAIw28IcxkI7VAKI48JMxC20s026xCa\n\tFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_Jr\n\tWlx4CE17CEb7AF67AKxVW8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j\n\t6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr\n\t0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUv\n\tcSsGvfC2KfnxnUUI43ZEXa7sREUDG3UUUUU==","X-CM-SenderInfo":"pzdqwylld63zxwud2x1vfou0bp/1tbiAQAKEWnTLbsAIAAAsW"},"content":"The first SoC in the UltraRISC series is UR-DP1000, containing octa\nUltraRISC C100 cores.\n\nSigned-off-by: Jia Wang \n---\n arch/riscv/Kconfig.socs | 9 +++++++++\n 1 file changed, 9 insertions(+)","diff":"diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs\nindex d621b85dd63b..98708569ec6a 100644\n--- a/arch/riscv/Kconfig.socs\n+++ b/arch/riscv/Kconfig.socs\n@@ -84,6 +84,15 @@ config ARCH_THEAD\n \thelp\n \t This enables support for the RISC-V based T-HEAD SoCs.\n \n+config ARCH_ULTRARISC\n+\tbool \"UltraRISC RISC-V SoCs\"\n+\thelp\n+\t This enables support for UltraRISC SoC platform hardware,\n+\t including boards based on the UR-DP1000.\n+\t UR-DP1000 is an 8-core 64-bit RISC-V SoC that supports\n+\t the RV64GCBHX ISA. It supports Hardware Virtualization\n+\t and RISC-V RV64 ISA H(v1.0) Extension.\n+\n config ARCH_VIRT\n \tbool \"QEMU Virt Machine\"\n \tselect POWER_RESET\n","prefixes":["v2","1/4"]}