{"id":2220246,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220246/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406182609.193886-17-pierrick.bouvier@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260406182609.193886-17-pierrick.bouvier@linaro.org>","date":"2026-04-06T18:26:05","name":"[v8,16/20] target/arm/tcg/arm_ldst.h: merge in translate.c","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"83ecbd6fcab308fcdc8f03c8eb533b3508037eab","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/1.1/people/85798/?format=json","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406182609.193886-17-pierrick.bouvier@linaro.org/mbox/","series":[{"id":498886,"url":"http://patchwork.ozlabs.org/api/1.1/series/498886/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498886","date":"2026-04-06T18:25:52","name":"target/arm: single-binary","version":8,"mbox":"http://patchwork.ozlabs.org/series/498886/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220246/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220246/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=iRb/kDL/;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x431.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Only translate.c uses those functions, thus move them back to this file.\n\nSigned-off-by: Pierrick Bouvier \n---\n target/arm/tcg/arm_ldst.h | 47 --------------------------------------\n target/arm/tcg/translate.c | 22 +++++++++++++++++-\n 2 files changed, 21 insertions(+), 48 deletions(-)","diff":"diff --git a/target/arm/tcg/arm_ldst.h b/target/arm/tcg/arm_ldst.h\nindex cee0548a1c7..e69de29bb2d 100644\n--- a/target/arm/tcg/arm_ldst.h\n+++ b/target/arm/tcg/arm_ldst.h\n@@ -1,47 +0,0 @@\n-/*\n- * ARM load/store instructions for code (armeb-user support)\n- *\n- * Copyright (c) 2012 CodeSourcery, LLC\n- *\n- * This library is free software; you can redistribute it and/or\n- * modify it under the terms of the GNU Lesser General Public\n- * License as published by the Free Software Foundation; either\n- * version 2.1 of the License, or (at your option) any later version.\n- *\n- * This library is distributed in the hope that it will be useful,\n- * but WITHOUT ANY WARRANTY; without even the implied warranty of\n- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU\n- * Lesser General Public License for more details.\n- *\n- * You should have received a copy of the GNU Lesser General Public\n- * License along with this library; if not, see .\n- */\n-\n-#ifndef ARM_LDST_H\n-#define ARM_LDST_H\n-\n-#include \"exec/translator.h\"\n-#include \"qemu/bswap.h\"\n-\n-/* Load an instruction and return it in the standard little-endian order */\n-static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,\n- target_ulong addr, bool sctlr_b)\n-{\n- return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));\n-}\n-\n-/* Ditto, for a halfword (Thumb) instruction */\n-static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,\n- target_ulong addr, bool sctlr_b)\n-{\n-#ifndef CONFIG_USER_ONLY\n- /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped\n- within each word. Undo that now. */\n- if (sctlr_b) {\n- addr ^= 2;\n- }\n-#endif\n- return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));\n-}\n-\n-#endif\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 6ea48efbac2..7fcf0656630 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -25,7 +25,6 @@\n #define TCG_ADDRESS_BITS 32\n #include \"tcg/tcg-op-mem.h\"\n #include \"qemu/log.h\"\n-#include \"arm_ldst.h\"\n #include \"semihosting/semihost.h\"\n #include \"cpregs.h\"\n #include \"exec/target_page.h\"\n@@ -6280,6 +6279,20 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)\n }\n }\n \n+/* Ditto, for a halfword (Thumb) instruction */\n+static inline uint16_t arm_lduw_code(CPUARMState *env, DisasContextBase* s,\n+ target_ulong addr, bool sctlr_b)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ /* In big-endian (BE32) mode, adjacent Thumb instructions have been swapped\n+ within each word. Undo that now. */\n+ if (sctlr_b) {\n+ addr ^= 2;\n+ }\n+#endif\n+ return translator_lduw_swap(env, s, addr, bswap_code(sctlr_b));\n+}\n+\n static bool insn_crosses_page(CPUARMState *env, DisasContext *s)\n {\n /* Return true if the insn at dc->base.pc_next might cross a page boundary.\n@@ -6514,6 +6527,13 @@ static void arm_post_translate_insn(DisasContext *dc)\n }\n }\n \n+/* Load an instruction and return it in the standard little-endian order */\n+static inline uint32_t arm_ldl_code(CPUARMState *env, DisasContextBase *s,\n+ target_ulong addr, bool sctlr_b)\n+{\n+ return translator_ldl_swap(env, s, addr, bswap_code(sctlr_b));\n+}\n+\n static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n","prefixes":["v8","16/20"]}