{"id":2220242,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2220242/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406182609.193886-20-pierrick.bouvier@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260406182609.193886-20-pierrick.bouvier@linaro.org>","date":"2026-04-06T18:26:08","name":"[v8,19/20] target/arm/tcg/translate.c: remove TARGET_AARCH64","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1ad7aaccfaf9b08ecbad39612d47f83a1cce416c","submitter":{"id":85798,"url":"http://patchwork.ozlabs.org/api/1.1/people/85798/?format=json","name":"Pierrick Bouvier","email":"pierrick.bouvier@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260406182609.193886-20-pierrick.bouvier@linaro.org/mbox/","series":[{"id":498886,"url":"http://patchwork.ozlabs.org/api/1.1/series/498886/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498886","date":"2026-04-06T18:25:52","name":"target/arm: single-binary","version":8,"mbox":"http://patchwork.ozlabs.org/series/498886/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2220242/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2220242/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=YDNqmZO0;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x534.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"We extract aarch64_translate_code function, and stub it accordingly.\n\nSuggested-by: Richard Henderson \nSigned-off-by: Pierrick Bouvier \n---\n target/arm/internals.h | 2 ++\n target/arm/tcg/stubs32.c | 7 +++++++\n target/arm/tcg/translate-a64.c | 8 ++++++++\n target/arm/tcg/translate.c | 19 ++++++++-----------\n 4 files changed, 25 insertions(+), 11 deletions(-)","diff":"diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 8ec27508473..2850edcb198 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);\n \n void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);\n void arm_translate_init(void);\n+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n+ int *max_insns, vaddr pc, void *host_pc);\n void arm_translate_code(CPUState *cs, TranslationBlock *tb,\n int *max_insns, vaddr pc, void *host_pc);\n \ndiff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\nindex c5a0bc61f47..3945dc49e5e 100644\n--- a/target/arm/tcg/stubs32.c\n+++ b/target/arm/tcg/stubs32.c\n@@ -3,6 +3,7 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"target/arm/internals.h\"\n #include \"target/arm/tcg/translate.h\"\n \n \n@@ -15,3 +16,9 @@ void a64_translate_init(void)\n {\n /* Don't initialize for 32 bits. Call site will be fixed later. */\n }\n+\n+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n+ int *max_insns, vaddr pc, void *host_pc)\n+{\n+ g_assert_not_reached();\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex ebab9f36f08..db3990576c0 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -10948,3 +10948,11 @@ const TranslatorOps aarch64_translator_ops = {\n .translate_insn = aarch64_tr_translate_insn,\n .tb_stop = aarch64_tr_tb_stop,\n };\n+\n+void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,\n+ int *max_insns, vaddr pc, void *host_pc)\n+{\n+ DisasContext dc = {};\n+ translator_loop(cpu, tb, max_insns, pc, host_pc,\n+ &aarch64_translator_ops, &dc.base, TCG_TYPE_I64);\n+}\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex aea38507ef4..9a971325144 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -6906,19 +6906,16 @@ static const TranslatorOps thumb_translator_ops = {\n void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n int *max_insns, vaddr pc, void *host_pc)\n {\n- DisasContext dc = { };\n- const TranslatorOps *ops = &arm_translator_ops;\n CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n- TCGType addr_type = is_a64(cpu_env(cpu)) ? TCG_TYPE_I64 : TCG_TYPE_I32;\n \n- if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n- ops = &thumb_translator_ops;\n- }\n-#ifdef TARGET_AARCH64\n if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {\n- ops = &aarch64_translator_ops;\n+ aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);\n+ } else {\n+ DisasContext dc = { };\n+ translator_loop(cpu, tb, max_insns, pc, host_pc,\n+ (EX_TBFLAG_AM32(tb_flags, THUMB)\n+ ? &thumb_translator_ops\n+ : &arm_translator_ops),\n+ &dc.base, TCG_TYPE_I32);\n }\n-#endif\n-\n- translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base, addr_type);\n }\n","prefixes":["v8","19/20"]}