{"id":2219737,"url":"http://patchwork.ozlabs.org/api/1.1/patches/2219737/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260404042015.86580-10-mohamed@unpredictable.fr/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260404042015.86580-10-mohamed@unpredictable.fr>","date":"2026-04-04T04:20:13","name":"[v6,09/11] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fdf8a7880917f8e1e26cefbbd6846b1aeb98968d","submitter":{"id":91318,"url":"http://patchwork.ozlabs.org/api/1.1/people/91318/?format=json","name":"Mohamed Mediouni","email":"mohamed@unpredictable.fr"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260404042015.86580-10-mohamed@unpredictable.fr/mbox/","series":[{"id":498696,"url":"http://patchwork.ozlabs.org/api/1.1/series/498696/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498696","date":"2026-04-04T04:20:05","name":"whpx: i386: bug fixes, feature probing and CPUID","version":6,"mbox":"http://patchwork.ozlabs.org/series/498696/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2219737/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2219737/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=F7C+hvoS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=outbound.st.icloud.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"When kernel-irqchip=on, manage TPR as part of the APIC state instead entirely.\n\nThis fixes some failure to set state errors.\n\nSigned-off-by: Mohamed Mediouni \n---\n target/i386/whpx/whpx-all.c | 37 ++++++++++++++++++++++---------------\n 1 file changed, 22 insertions(+), 15 deletions(-)","diff":"diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 97284b954b..a3e91ca533 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -93,7 +93,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n WHvX64RegisterCr2,\n WHvX64RegisterCr3,\n WHvX64RegisterCr4,\n- WHvX64RegisterCr8,\n \n /* X64 Debug Registers */\n /*\n@@ -457,8 +456,11 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n vcxt.values[idx++].Reg64 = env->cr[3];\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n vcxt.values[idx++].Reg64 = env->cr[4];\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- vcxt.values[idx++].Reg64 = vcpu->tpr;\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ WHV_REGISTER_VALUE cr8 = {.Reg64 = vcpu->tpr};\n+ whpx_set_reg(cpu, WHvX64RegisterCr8, cr8);\n+ }\n \n /* 8 Debug Registers - Skipped */\n \n@@ -714,11 +716,14 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n env->cr[3] = vcxt.values[idx++].Reg64;\n assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n env->cr[4] = vcxt.values[idx++].Reg64;\n- assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n- tpr = vcxt.values[idx++].Reg64;\n- if (tpr != vcpu->tpr) {\n- vcpu->tpr = tpr;\n- cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+\n+ /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+ if (!whpx_irqchip_in_kernel()) {\n+ tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (tpr != vcpu->tpr) {\n+ vcpu->tpr = tpr;\n+ cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+ }\n }\n \n /* 8 Debug Registers - Skipped */\n@@ -1660,7 +1665,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n \n /* Sync the TPR to the CR8 if was modified during the intercept */\n tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n- if (tpr != vcpu->tpr) {\n+ if (!whpx_irqchip_in_kernel() && tpr != vcpu->tpr) {\n vcpu->tpr = tpr;\n reg_values[reg_count].Reg64 = tpr;\n qatomic_set(&cpu->exit_request, true);\n@@ -1707,12 +1712,14 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n \n env->eflags = vcpu->exit_ctx.VpContext.Rflags;\n \n- uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n- if (vcpu->tpr != tpr) {\n- vcpu->tpr = tpr;\n- bql_lock();\n- cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n- bql_unlock();\n+ if (!whpx_irqchip_in_kernel()) {\n+ uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n+ if (vcpu->tpr != tpr) {\n+ vcpu->tpr = tpr;\n+ bql_lock();\n+ cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n+ bql_unlock();\n+ }\n }\n \n vcpu->interruption_pending =\n","prefixes":["v6","09/11"]}