{"id":2233390,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2233390/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/cover/20260506015845.2306182-1-pan2.li@intel.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260506015845.2306182-1-pan2.li@intel.com>","date":"2026-05-06T01:57:09","name":"[v1,0/2] RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost","submitter":{"id":86320,"url":"http://patchwork.ozlabs.org/api/1.1/people/86320/?format=json","name":"Li, Pan2","email":"pan2.li@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/gcc/cover/20260506015845.2306182-1-pan2.li@intel.com/mbox/","series":[{"id":502962,"url":"http://patchwork.ozlabs.org/api/1.1/series/502962/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=502962","date":"2026-05-06T01:57:10","name":"RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost","version":1,"mbox":"http://patchwork.ozlabs.org/series/502962/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2233390/comments/","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=Cnsi7D2p;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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d=\"scan'208\";a=\"96484863\""],"X-ExtLoop1":"1","From":"pan2.li@intel.com","To":"gcc-patches@gcc.gnu.org","Cc":"juzhe.zhong@rivai.ai, kito.cheng@gmail.com, jeffreyalaw@gmail.com,\n rdapp.gcc@gmail.com, ken.chen@intel.com, hongtao.liu@intel.com,\n Pan Li ","Subject":"[PATCH v1 0/2] RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx\n on GR2VR cost","Date":"Wed, 6 May 2026 09:57:09 +0800","Message-ID":"<20260506015845.2306182-1-pan2.li@intel.com>","X-Mailer":"git-send-email 2.43.0","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org"},"content":"From: Pan Li \n\nThis patch series would like to introduce the combine of\nvec_dup + vmsgt.vv into vmsgt.vx on the cost value of GR2VR.\nThe late-combine will take place if the cost of GR2VR like\n1, 2, 15 in test.\n\nFrom:\n | ...\n | vmv.v.x\n | L1:\n | vmsgt.vv\n | J L1\n | ...\n\nTo:\n | ...\n | L1:\n | vmsgt.vx\n | J L1\n | ...\n\nThe below test suites are passed for this patch series.\n* The rv64gcv fully regression test.\n\nPan Li (2):\n RISC-V: Combine vec_duplicate + vmsgt.vv to vmsgt.vx on GR2VR cost\n RISC-V: Add test for vec_duplicate + vmsgt.vv combine with GR2VR cost 0, 1 and 15\n\n gcc/config/riscv/predicates.md | 2 +-\n gcc/config/riscv/riscv-v.cc | 2 +\n .../riscv/rvv/autovec/vx_vf/vx-1-i16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-i32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-i64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-i8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-i8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-i8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary.h | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 136 ++++++++++++++++++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c | 15 ++\n 20 files changed, 212 insertions(+), 1 deletion(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i32.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i64.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgt-run-1-i8.c"}