{"id":2231046,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2231046/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260430094238.987976-1-grzegorz.nitka@intel.com/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.1/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430094238.987976-1-grzegorz.nitka@intel.com>","date":"2026-04-30T09:42:30","name":"[v7,net-next,0/8] dpll/ice: Add generic DPLL type and full TX reference clock control for E825","submitter":{"id":82711,"url":"http://patchwork.ozlabs.org/api/1.1/people/82711/?format=json","name":"Nitka, Grzegorz","email":"grzegorz.nitka@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260430094238.987976-1-grzegorz.nitka@intel.com/mbox/","series":[{"id":502259,"url":"http://patchwork.ozlabs.org/api/1.1/series/502259/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=502259","date":"2026-04-30T09:42:30","name":"dpll/ice: Add generic DPLL type and full TX reference clock control for E825","version":7,"mbox":"http://patchwork.ozlabs.org/series/502259/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2231046/comments/","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=ODlOzS86;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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a=\"82342551\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"82342551\"","E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"272649722\""],"X-ExtLoop1":"1","From":"Grzegorz Nitka ","To":"netdev@vger.kernel.org","Date":"Thu, 30 Apr 2026 11:42:30 +0200","Message-Id":"<20260430094238.987976-1-grzegorz.nitka@intel.com>","X-Mailer":"git-send-email 2.39.3","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Mailman-Original-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777542400; x=1809078400;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=uVyXpORKtKxQUy4UyJaNWTGTd0GDPD7WkYn7lyfK/II=;\n b=QhMyzWt35DJeXuq+xJRTb4r9w50Ou9IVKF8R8J9g856SRStl04p/SGow\n TqNesUeXjSYnYLUp3QcOfTA6WNKMHsagYxRDzKrrnWyl3qCWYFh2epWnE\n QVOxA6p9RuoyeDbcjIZagMR+08R93V+qaRxm3nMMy2na7DsYFsg/NalIP\n Ptgy+vhA41CgwbZ4VFiGzGBxJ535ZMhL/7mDDbSnvrZ/yRYiPgWDY01dA\n 7EKsW4U+MTj89/LsfgjIfYfpwrnMVfrXXIzcG9bqe2w2H79rej/quRixp\n tKh4108n/V05lnFYq60Jywy1Cy4631IhxHK3ra5FINgowMfhZpZ1Da4zV\n Q==;","X-Mailman-Original-Authentication-Results":["smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com","smtp3.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=QhMyzWt3"],"Subject":"[Intel-wired-lan] [PATCH v7 net-next 0/8] dpll/ice: Add generic\n DPLL type and full TX reference clock control for E825","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Cc":"ivecera@redhat.com, vadim.fedorenko@linux.dev, kuba@kernel.org,\n jiri@resnulli.us, edumazet@google.com, przemyslaw.kitszel@intel.com,\n richardcochran@gmail.com, donald.hunter@gmail.com,\n linux-kernel@vger.kernel.org, arkadiusz.kubalewski@intel.com,\n andrew+netdev@lunn.ch, intel-wired-lan@lists.osuosl.org, horms@kernel.org,\n Prathosh.Satish@microchip.com, anthony.l.nguyen@intel.com, pabeni@redhat.com,\n davem@davemloft.net","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"NOTE: This series is intentionally submitted on net-next (not\nintel-wired-lan) as early feedback of DPLL subsystem changes is\nwelcomed. In the past possible approaches were discussed in [1].\n\nThis series adds TX reference clock support for E825 devices and exposes\nTX clock selection and synchronization status via the Linux DPLL\nsubsystem.\n\nHere is the high-level connection diagram for E825 device:\n +------------------------------------------------------------------+\n | |\n | +-----------------------------+ |\n | | | |\n | | MAC | |\n | |+------------+-----+ | |\n | ||RX/1588 |PHC|tspll<----\\ | |\n+---+----+ ||MUX +---+-^---| | | |\n| E | RX >---------------------> | >--\\ | | |\n| T | | /----------------> | >-\\| | | |\n| H |----+ | |+---------+----^---+ || | | |\n| 1 | TX <----|----------------+TX MUX < OCXO | || | | |\n| |PLL | | || |--------| || | | |\n+---+----+ | /----+ <-ext_ref<-||-|----|------ext_ref\n| E | RX >----/ | || |--------+ || | | |\n| T | | | || < SyncE | || | | |\n| H |----+ | |+-----------^------+ || | | |\n| 2 | TX <----------------/ | | /------||-/ | |\n| |PLL | +------------|-|------||------+ |\n+---+----+ /--/ | || |\n| . | RX >--- | | || |\n| . | | +----------|----|------||--+ |\n| . |----+ | +-^-+--^+ || | |\n| | TX <--- | |EEC|PPS| || | |\n| |PLL | | +-------+ || | |\n+---+----+ | | <-CLK0/| | |\n| E | RX >--- | | DPLL | | | |\n| T | | | | <-CLK1-/ | |\n| H |----+ | | | | |\n| X | TX <--- | | <---SMA---< |\n| |PLL | | | | | |\n+---+----+ | | <---GPS---< |\n | | | | | |\n | | | <---...---< |\n | | | | | |\n | | +-------+ | |\n | | External timing module | |\n | +--------------------------+ |\n +------------------------------------------------------------------+\n\nE825 hardware contains a dedicated TX clock domain with per-port source\nselection behavior that is distinct from PPS handling and from board-level\nEEC distribution. TX reference clock selection is device-wide, shared\nacross ports, and mediated by firmware as part of link bring-up. As a\nresult, TX clock selection intent may differ from effective hardware\nconfiguration, and software must verify outcome after link-up.\n\nTo support this, the series extends the DPLL core and the ice driver\nincrementally. The series also introduces DPLL_TYPE_GENERIC as a broad\nUAPI class for DPLL instances outside PPS/EEC categories. The intent is\nto keep type naming reusable and scalable across different ASIC\ntopologies while preserving functional discoverability via\ndriver/device context and pin topology.\n\nThis follows netdev discussion guidance that UAPI type naming should avoid\nlocation-specific or vendor-specific taxonomy, because such labels do not\nscale across different ASIC designs. The function of a given DPLL instance\nis already discoverable from driver/device context and pin topology, and\ndoes not require an additional narrow type identifier in UAPI.\n\nAt the same time, a separate DPLL object is still needed for E825 TX clock\ncontrol/reporting semantics. Using DPLL_TYPE_GENERIC provides a reusable\nclass for devices outside PPS/EEC without overfitting UAPI naming to one\ntopology.\n\nThe relevant discussion is in [2].\n\nSeries content\n- add a new generic DPLL type for devices outside PPS/EEC classes;\n- relax DPLL pin registration rules for firmware-described shared pins\n and extend pin notifications with a source identifier;\n- allow dynamic state control of SyncE reference pins where hardware\n supports it;\n- add CPI infrastructure for PHY-side TX clock control on E825C;\n- introduce a TX-clock DPLL device and TX reference clock pins\n (EXT_EREF0 and SYNCE) in the ice driver;\n- extend the Restart Auto-Negotiation command to carry a TX reference\n clock index;\n- implement hardware-backed TX reference clock switching, post-link\n verification, and TX synchronization reporting.\n\nTXCLK pins report TX reference topology only. Actual synchronization\nsuccess is reported via DPLL lock status, updated after hardware\nverification: external TX references report LOCKED, while the internal\nENET/TXCO source reports UNLOCKED.\n\nThis provides reliable TX reference selection and observability on E825\ndevices using standard DPLL interfaces, without conflating user intent\nwith effective hardware behavior.\n\n[1] https://lore.kernel.org/netdev/20250905160333.715c34ac@kernel.org/\n[2] https://lore.kernel.org/netdev/20260402230626.3826719-1-grzegorz.nitka@intel.com/\n\nChanges in v7:\n- rebased\n- replace TXC-specific DPLL type with DPLL_TYPE_GENERIC (patch 1/8)\n- update TXC framework to use DPLL_TYPE_GENERIC instead of DPLL_TYPE_GENERIC\n (patch 5/8)\n- AI-review: added short trailing comment to the local mutex declaration\n to satisfy checkpatch report (patch 6/8)\n\nChanges in v6:\n - rebased\n - AI-review: fix unprotected concurrent access to shared clock\n bitmap (patch 8/8)\n - AI-review: fix potential issue in tx-clk pin state request handling\n ('already set' early-exit based now on tx_clk_req comparison, patch 8/8)\n - AI-review: CPI transaction serialization (patch 6/8) \n\nChanges in v5:\n - rebased\n - reworded cover letter\n - replace 'ntfy_src' new argument name with 'src_clk_id' and use it\n consistently in DPLL notification calls (patch 3/8)\n - reworded commit message (patch 5/8)\n - use FIELD_PREP/GENMSK macros instead of struct bitfields (patch 6/8)\n - reworded commit message (patch 5/8, patch 8/8)\n - refactor the code to avoid sleeping while DPLL mutex is held (using\n work_queue, patch 8/8)\n - added TXCLK pins and TXC DPLL notifications (patch 8/8)\n - removed 'unused clock disable' mechanism from the scope of this series\n\nChanges in v4:\n - rebased\n - edited, shortened the commit message in 3/8 patch\n - moved ice_get_ctrl_pf to the header file (patch 8/8) and\n removed duplicated static definitions from ice_ptp and ice_txlck\n modules\n - add NULL/invalid pointer checker for returned pointer from\n ice_get_ctrl_pf (patch 8/8)\n - edited error message in case AN restart failure (patch 8/8)\n\nChanges in v3:\n- improved commit message (patch 1/8, AI review comment)\n- improved deinitialization path in ice_dpll_deinit_txclk_pins to\n avoid potential NULL dereference. NULL checking moved to\n ice_dpll_unregister_pins (patch 5/8, found by AI review)\n- removed redundant semicolon (patch 6/8)\n\nChanges in v2:\n- rebased\n- added autogenerated DPLL files (patch 1/8)\n- fixed checkpatch 'parenthesis alignment' warning (patch 2/8)\n- fixed error path in ice_dpll_init_txclk_pins (AI warning, patch 5/8)\n- fixed kdoc warnings (patch 6/8, patch 8/8)\n\nGrzegorz Nitka (8):\n dpll: add generic DPLL type\n dpll: allow registering FW-identified pin with a different DPLL\n dpll: extend pin notifier and netlink events with notification source\n ID\n dpll: zl3073x: allow SyncE_Ref pin state change\n ice: introduce TXC DPLL device and TX ref clock pin framework for E825\n ice: implement CPI support for E825C\n ice: add Tx reference clock index handling to AN restart command\n ice: implement E825 TX ref clock control and TXC hardware sync status\n\n .../devicetree/bindings/dpll/dpll-device.yaml | 2 +-\n Documentation/netlink/specs/dpll.yaml | 3 +\n drivers/dpll/dpll_core.c | 32 +-\n drivers/dpll/dpll_core.h | 3 +-\n drivers/dpll/dpll_netlink.c | 10 +-\n drivers/dpll/dpll_netlink.h | 4 +-\n drivers/dpll/dpll_nl.c | 2 +-\n drivers/dpll/zl3073x/prop.c | 9 +\n drivers/net/ethernet/intel/ice/Makefile | 2 +-\n drivers/net/ethernet/intel/ice/ice.h | 12 +\n drivers/net/ethernet/intel/ice/ice_adapter.c | 4 +\n drivers/net/ethernet/intel/ice/ice_adapter.h | 7 +\n .../net/ethernet/intel/ice/ice_adminq_cmd.h | 2 +\n drivers/net/ethernet/intel/ice/ice_common.c | 5 +-\n drivers/net/ethernet/intel/ice/ice_common.h | 2 +-\n drivers/net/ethernet/intel/ice/ice_cpi.c | 364 +++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_cpi.h | 61 +++\n drivers/net/ethernet/intel/ice/ice_dpll.c | 380 ++++++++++++++++--\n drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +\n drivers/net/ethernet/intel/ice/ice_lib.c | 3 +-\n drivers/net/ethernet/intel/ice/ice_ptp.c | 26 +-\n drivers/net/ethernet/intel/ice/ice_ptp.h | 7 +\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 37 ++\n drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 34 ++\n drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 5 +-\n drivers/net/ethernet/intel/ice/ice_txclk.c | 251 ++++++++++++\n drivers/net/ethernet/intel/ice/ice_txclk.h | 38 ++\n drivers/net/ethernet/intel/ice/ice_type.h | 2 +\n include/linux/dpll.h | 1 +\n include/uapi/linux/dpll.h | 2 +\n 30 files changed, 1266 insertions(+), 54 deletions(-)\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.h\n create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_txclk.h\n\n\nbase-commit: 790ead9394860e7d70c5e0e50a35b243e909a618"}