{"id":2230991,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2230991/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/cover/20260430093422.74812-1-biju.das.jz@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430093422.74812-1-biju.das.jz@bp.renesas.com>","date":"2026-04-30T09:34:05","name":"[v4,0/7] Add Renesas RZ/G3L PINCONTROL support","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/cover/20260430093422.74812-1-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":502254,"url":"http://patchwork.ozlabs.org/api/1.1/series/502254/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502254","date":"2026-04-30T09:34:06","name":"Add Renesas RZ/G3L PINCONTROL support","version":4,"mbox":"http://patchwork.ozlabs.org/series/502254/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2230991/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=aJr1URz4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"From: Biju Das \n\nHi All,\n\nThis patch series aims to add basic pin-control support for the Renesas\nRZ/G3L SoC. The RZ/G3L pinctrl has an OTHER_POC register compared to other\nSoCs for setting the IO domain voltage for AWO, ISO, and WDT.\n\nDocument the bindings for the RZ/G3L SoC and add pinctrl definitions in\nthe driver. Some IPs need to set the register IPCONT_SEL_CLONECH in SYSC\nto control the clone channel of the IP.\n\nv3->v4:\n * Dropped patch#1 and #3 from the series as it is accepted.\n * Dropped Port P4 from binding header as it does not exist on RZ/G3L SoC.\n * Retained the tag for bindings as it is trivial change.\n * Added a patch to make QSPI register handling conditional.\n * Updated commit description for patch#3.\n * Updated rzg2l_caps_to_pwr_reg() to return mask in addition to register\n offset.\n * Dropped ffs(), using field_get() instead to get PoC offset in\n rzg2l_get_power_source().\n * Simplified rzg2l_set_power_source() by using mask from\n rzg2l_caps_to_pwr_reg().\n * Added scoped_guard() for RMW operation in rzg2l_set_power_source().\n * Added a patch to update rzg2l_pin_to_oen_bit() so that it can reuse on\n RZ/G3L.\n * Dropped extra white spaces in SD0_CLK and SD0_DATA0 entries.\n * Renamed SD0_DATA* → SD0_DAT* to match the pin function spreadsheet.\n * Renamed SCIF_{RXD,TXD} → SCIF0_{RXD,TXD} to match the pin function\n spreadsheet.\n * .pin_to_oen_bit = rzg2l_pin_to_oen_bit() and dropped oen_max_port from\n rzg3l_hwcfg.\n * Updated the data type of func varaible from u8 to unsigned int.\n * Collected the tag.\n * Started using an 8-bit pin mask instead of start and end pin indices,\n and combined multiple entries with the same port number and config\n using ORed values of BIT() and GENMASK(), thereby reducing table size.\n * Started using an 8-bit function mask instead of a function index, and\n got rid of the shared pin bit. This also provides info about the\n possible functions.\n * Dropped RZG3L_CLONE_CHANNEL_{PACK,DTAT,SHARED_PIN_MASK} macros.\n * Replaced RZG3L_CLONE_CHANNEL_CFG_PIN_{START,END}_MASK macro with\n RZG3L_CLONE_CHANNEL_PIN_MASK.\n * Replaced RZG3L_CLONE_CHANNEL_CFG_PORT_MASK macro with\n RZG3L_CLONE_CHANNEL_PORT_MASK.\n * Updated kernel doc comment for clone register from 'registers' to\n 'register'.\n * Dropped dynamic allocation for the clone register cache, instead using\n static allocation in struct rzg2l_pinctrl_reg_cache, as it is a single\n 32-bit register.\n * Replaced the LUT and for loop in rzg2l_pinctrl_set_clone_mode() with a\n simple switch statement.\n * Dropped the complex check to find the func match in\n rzg2l_pinctrl_set_clone_mode() by using pin_func_mask & BIT(func).\n * Dropped the inner for loop for finding a pin match in\n rzg2l_pinctrl_set_clone_mode() by using pin_mask & BIT(pin).\n * Dropped field_prep with \"val << bit\" in rzg2l_pinctrl_set_clone_mode()\n as val is just 0 or 1.\n * In rzg2l_pinctrl_probe(), replaced the temporary variable offset with\n &pctrl->clone_offset.\n * Replaced RZG3L_CLONE_CHANNEL_PIN_CFG_PACK with RZG3L_CLONE_CHANNEL_DATA,\n and replaced clone_pin_configs, n_clone_pins,\n r9a08g046_clone_channel_pin_cfg with clone_channel_data,\n n_clone_channel_data, and r9a08g046_clone_channel_data.\nv2->v3:\n * Dropped clk, pincontrol device node and pincontrol support for SCIF0\n and GBETH nodes from this series. Will add this later.\n * Documented renesas,clonech property for controlling clone channel\n control register located on SYSC IP block on RZ/G3L SoC.\n * Retained the tag as it is similar change for RZ/G3E thermal bindings.\n * Updated r9a08g046_gpio_configs[] by replacing the typo AWO->ISO.\n * Added PIN_CFG_PUPD to RZG3L_MPXED_ETH_PIN_FUNCS macro\n * Replaced RZG2L_MPXED_COMMON_PIN_FUNCS->RZG3L_MPXED_PIN_FUNCS in \n RZG3L_MPXED_PIN_FUNCS_POC macro for setting power source for pins.\n * Added clone channel control support in the driver\nv1->v2:\n * Split DTSI patches from bindings\n * Fix typo maxItems->minItems in bindings\n * Collected the tag\n\nBiju Das (7):\n dt-bindings: pinctrl: renesas: Document RZ/G3L SoC\n pinctrl: renesas: rzg2l: Make QSPI register handling conditional\n pinctrl: renesas: rzg2l: Add support for selecting power source for\n {WDT,AWO,ISO}\n pinctrl: renesas: rzg2l: Update OEN pin validation to use exact match\n pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC\n pinctrl: renesas: rzg2l: Simplify rzg2l_pinctrl_set_mux()\n pinctrl: renesas: rzg2l: Add support for clone channel control\n\n .../pinctrl/renesas,rzg2l-pinctrl.yaml | 20 +\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 485 +++++++++++++++++-\n .../pinctrl/renesas,r9a08g046-pinctrl.h | 38 ++\n 3 files changed, 526 insertions(+), 17 deletions(-)\n create mode 100644 include/dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h"}