{"id":2230720,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2230720/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260430002046.59739-1-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260430002046.59739-1-richard.henderson@linaro.org>","date":"2026-04-30T00:19:59","name":"[v3,00/47] target/arm: Implement FEAT_FP8","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.1/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260430002046.59739-1-richard.henderson@linaro.org/mbox/","series":[{"id":502175,"url":"http://patchwork.ozlabs.org/api/1.1/series/502175/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175","date":"2026-04-30T00:20:06","name":"target/arm: Implement FEAT_FP8","version":3,"mbox":"http://patchwork.ozlabs.org/series/502175/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2230720/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=cjLOJsBp;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zc54gVbz1yHZ\n\tfor ; Thu, 30 Apr 2026 10:21:57 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wIF9K-0006IA-5O; Wed, 29 Apr 2026 20:21:02 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wIF9E-0006GA-1R\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:20:57 -0400","from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wIF9C-00063i-1l\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:20:55 -0400","by mail-pf1-x42c.google.com with SMTP id\n d2e1a72fcca58-82f4a53ae20so246366b3a.3\n for ; Wed, 29 Apr 2026 17:20:53 -0700 (PDT)","from stoup.. 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Rebase on softfloat-parts.h, which allows us to drop some\n local changes to fpu/.\n - Enable ID_AA64FPFR0.F8{E5M2,E4M3}.\n - Implement FEAT_SME_LUTv2.\n - Implement FEAT_FP8FMA, FEAT_SSVE_FP8FMA.\n\nI still haven't addressed the required firmware update for\n\n tests/functional/aarch64/test_rme_virt.py\n tests/functional/aarch64/test_rme_sbsaref.py\n\n\nr~\n\n\nCc: pierrick.bouvier@oss.qualcomm.com\nCc: alex.bennee@linaro.org\n\n\nRichard Henderson (47):\n target/arm: Implement ID_AA64ISAR3\n target/arm: Implement FEAT_FAMINMAX for AdvSIMD\n target/arm: Implement FEAT_FAMINMAX for SME\n target/arm: Implement FEAT_FAMINMAX for SVE\n target/arm: Enable FEAT_FAMINMAX for -cpu max\n target/arm: Update SCR bits for Arm ARM M.a.a\n target/arm: Update HCRX bits for Arm ARM M.a.a\n target/arm: Introduce FPMR\n target/arm: Update SCTLR bits for FEAT_FPMR\n target/arm: Enable EnFPM bits for FEAT_FPMR\n target/arm: Clear FPMR on ResetSVEState\n target/arm: Add FPMR_EL to TBFLAGS\n target/arm: Trap direct acceses to FPMR\n target/arm: Enable FEAT_FPMR for -cpu max\n target/arm: Implement ID_AA64FPFR0\n target/arm: Add isar_feature_aa64_f8cvt\n target/arm: Implement FSCALE for AdvSIMD\n target/arm: Implement FSCALE for SME\n target/arm: Split vector-type.h from cpu.h\n target/arm: Move vectors_overlap to vec_internal.h\n target/arm: Implement BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2 for AdvSIMD\n target/arm: Implement BF1CVT, BF1CVTLT, BF2CVT, BF2CVTLT for SVE\n target/arm: Rename SME BFCVT patterns to BFCVT_hs\n target/arm: Implement BF1CVT, BF1CVTL, BF2CVT, BF2CVTL for SME\n target/arm: Implement F1CVTL, F1CVTL2, F2CVTL, F2CVTL2 for AdvSIMD\n target/arm: Implement F1CVT, F1CVTLT, F2CVT, F2CVTLT for SVE\n target/arm: Implement F1CVT, F1CVTL, F2CVT, F2CVTL for SME\n target/arm: Implement BFCVTN for SVE\n target/arm: Implement FCVTN (16- to 8-bit fp) for AdvSIMD\n target/arm: Implement FCVTN, FCVTN2 (32- to 8-bit fp) for AdvSIMD\n target/arm: Implement FCVTN (16- to 8-bit fp) for SVE\n target/arm: Implement FCVTNB, FCVTNT for SVE\n target/arm: Implement FCVT (FP16 to FP8) for SME\n target/arm: Implement FCVT, FCVTN (FP32 to FP8) for SME\n target/arm: Implement LUTI2, LUTI4 for AdvSIMD\n target/arm: Implement LUTI2, LUTI4 for SVE\n target/arm: Enable FEAT_LUT for -cpu max\n target/arm: Enable FEAT_FP8 for -cpu max\n target/arm: Update ID_AA64SMFR0_EL1 fields to ARM M.b\n target/arm: Implement MOVT (vector to table)\n target/arm: Implement LUTI4 (four registers, 8-bit)\n target/arm: Enable FEAT_SME_LUTv2 for -cpu max\n target/arm: Implement FMLALB, FMLALT for AdvSIMD\n target/arm: Implement FMLALB, FMLALT (FP8 to FP16) for SVE\n target/arm: Implement FMLALL{BB,BT,TB,TT} for AdvSIMD\n target/arm: Implement FMLALL{BB,BT,TB,TT} for SVE\n target/arm: Enable FEAT_FP8FMA, FEAT_SSVE_FP8FMA for -cpu max\n\n target/arm/cpregs.h | 5 +\n target/arm/cpu-features.h | 97 +++\n target/arm/cpu.h | 52 +-\n target/arm/helper-fp8.h | 14 +\n target/arm/internals.h | 13 +-\n target/arm/tcg/helper-a64-defs.h | 11 +\n target/arm/tcg/helper-defs.h | 6 +\n target/arm/tcg/helper-fp8-defs.h | 31 +\n target/arm/tcg/helper-sme-defs.h | 2 +-\n target/arm/tcg/helper-sve-defs.h | 14 +\n target/arm/tcg/translate-a64.h | 1 +\n target/arm/tcg/translate.h | 10 +\n target/arm/tcg/vec_internal.h | 19 +\n target/arm/vector-type.h | 44 ++\n target/arm/helper.c | 43 +-\n target/arm/machine.c | 20 +\n target/arm/tcg/cpu64.c | 18 +\n target/arm/tcg/fp8_helper.c | 1036 ++++++++++++++++++++++++++++++\n target/arm/tcg/hflags.c | 41 ++\n target/arm/tcg/sme_helper.c | 8 +-\n target/arm/tcg/sve_helper.c | 8 +\n target/arm/tcg/translate-a64.c | 152 +++++\n target/arm/tcg/translate-sme.c | 109 +++-\n target/arm/tcg/translate-sve.c | 147 +++++\n target/arm/tcg/vec_helper.c | 66 ++\n target/arm/tcg/vec_helper64.c | 51 ++\n docs/system/arm/emulation.rst | 7 +\n target/arm/cpu-sysregs.h.inc | 2 +\n target/arm/tcg/a64.decode | 38 ++\n target/arm/tcg/meson.build | 1 +\n target/arm/tcg/sme.decode | 36 +-\n target/arm/tcg/sve.decode | 41 +-\n 32 files changed, 2084 insertions(+), 59 deletions(-)\n create mode 100644 target/arm/helper-fp8.h\n create mode 100644 target/arm/tcg/helper-fp8-defs.h\n create mode 100644 target/arm/vector-type.h\n create mode 100644 target/arm/tcg/fp8_helper.c"}