{"id":2229984,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2229984/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/cover/20260429035134.1023330-1-happycpu@gmail.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260429035134.1023330-1-happycpu@gmail.com>","date":"2026-04-29T03:51:32","name":"[v2,0/2] gpio: 74x164: seed the chain from DT at probe time","submitter":{"id":93205,"url":"http://patchwork.ozlabs.org/api/1.1/people/93205/?format=json","name":"Chanhong Jung","email":"happycpu@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/cover/20260429035134.1023330-1-happycpu@gmail.com/mbox/","series":[{"id":501979,"url":"http://patchwork.ozlabs.org/api/1.1/series/501979/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501979","date":"2026-04-29T03:51:32","name":"gpio: 74x164: seed the chain from DT at probe time","version":2,"mbox":"http://patchwork.ozlabs.org/series/501979/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2229984/comments/","headers":{"Return-Path":"\n <linux-gpio+bounces-35744-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=rxx+i8wn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; helo=sto.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35744-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"rxx+i8wn\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.210.169","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g53Jf1bFbz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 13:51:46 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 3DA8C30039BA\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 03:51:43 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 2AE1231A7E2;\n\tWed, 29 Apr 2026 03:51:40 +0000 (UTC)","from mail-pf1-f169.google.com (mail-pf1-f169.google.com\n [209.85.210.169])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id B7C8514F70\n\tfor <linux-gpio@vger.kernel.org>; Wed, 29 Apr 2026 03:51:38 +0000 (UTC)","by mail-pf1-f169.google.com with SMTP id\n d2e1a72fcca58-834da62e52dso911086b3a.3\n        for <linux-gpio@vger.kernel.org>;\n Tue, 28 Apr 2026 20:51:38 -0700 (PDT)","from happycpu-p1.. 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That sidesteps\nboth the v1 review concerns at once: there is no vendor-specific\nproperty to argue about, and the bit-N-equals-line-N convention is\nalready documented for nxp,pcf8575.\n\nBackground (carried over from v1):\nThe 74HC595 / 74LVC594 family is push-pull output only. There is no\nread-back path, no defined power-on state for the parallel outputs, and\n__gen_74x164_write_config() always shifts the full chain on every\ntransaction. The driver therefore publishes whatever sits in\nchip->buffer on the very first ->set() call, and today that buffer is\nfresh from kzalloc(), so all outputs come up low. On boards with active-\nlow indicators or other signals whose initial level matters, the 0x00\npublish glitches the chain before user space (or gpio-leds default-state\nwalking) gets a chance to run.\n\ngpio-hog is not a substitute here: each hog is applied sequentially and\nforces an intermediate full-chain write per line, and on this board\ngpio-leds already claims every output, leaving no free lines to hog.\n\nApproach in v2:\nPatch 1 documents the existing lines-initial-states property under the\nfairchild,74hc595 binding, with the small wording change that on this\noutput-only family bit=0 drives the line low and bit=1 drives it high.\n\nPatch 2 wires the driver to read that bitmask into chip->buffer before\nthe first __gen_74x164_write_config(), so the chain comes up in the\nconfigured pattern atomically on the first SPI transaction. Property\nabsence keeps the existing zeroing behaviour.\n\nThe bitmask covers up to 32 lines (four cascaded chips), which fits all\nexisting in-tree users and the typical 1-4 chip cascades. If a longer\nchain ever needs seeding, the property can be extended to a uint32-array\nwithout breaking the bit-N-equals-line-N convention.\n\nTested on a 4-chip 74HC595 chain (32 outputs, active-low LEDs); the\n0x00 glitch on first write goes away with lines-initial-states set to\nthe desired idle pattern, and absence of the property leaves behaviour\nunchanged.\n\nChanges since v1\n[https://lore.kernel.org/linux-gpio/cover.1776872453.git.happycpu@gmail.com/]:\n  - Drop the new 'registers-default' u8-array property; reuse the\n    existing 'lines-initial-states' uint32 bitmask instead, as\n    suggested by Linus Walleij. This also addresses Krzysztof\n    Kozlowski's concern about adding a generic, non-vendor-prefixed\n    property to a vendor-specific binding (the property is already\n    documented for nxp,pcf8575).\n  - Driver now reads a single u32 and maps bit N to GPIO line N,\n    matching the nxp,pcf8575 convention. For this output-only device\n    the polarity is the natural one: bit=0 drives the line low,\n    bit=1 drives it high.\n  - Binding example updated accordingly.\n\nChanhong Jung (2):\n  dt-bindings: gpio: fairchild,74hc595: add lines-initial-states\n    property\n  gpio: 74x164: support lines-initial-states for boot-time output state\n\n .../bindings/gpio/fairchild,74hc595.yaml        | 13 +++++++++++++\n drivers/gpio/gpio-74x164.c                      | 17 ++++++++++++++++-\n 2 files changed, 29 insertions(+), 1 deletion(-)"}