{"id":2229333,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2229333/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/cover/20260428072746.3641227-1-pan2.li@intel.com/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.1/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428072746.3641227-1-pan2.li@intel.com>","date":"2026-04-28T07:26:25","name":"[v1,0/2] RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost","submitter":{"id":86320,"url":"http://patchwork.ozlabs.org/api/1.1/people/86320/?format=json","name":"Li, Pan2","email":"pan2.li@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/gcc/cover/20260428072746.3641227-1-pan2.li@intel.com/mbox/","series":[{"id":501773,"url":"http://patchwork.ozlabs.org/api/1.1/series/501773/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=501773","date":"2026-04-28T07:26:25","name":"RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost","version":1,"mbox":"http://patchwork.ozlabs.org/series/501773/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2229333/comments/","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=RIHp3NUs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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The late-combine will\ntake place if the cost of GR2VR like 1, 2, 15 in test.\n\nFrom:\n | ...\n | vmv.v.x\n | L1:\n | vmsgtu.vv\n | J L1\n | ...\n\nTo:\n | ...\n | L1:\n | vmsgtu.vx\n | J L1\n | ...\n\nThe below test suites are passed for this patch series.\n* The rv64gcv fully regression test.\n\nPan Li (2):\n RISC-V: Combine vec_duplicate + vmsgtu.vv to vmsgtu.vx on GR2VR cost\n RISC-V: Add test for vec_duplicate + vmsgtu.vv combine with GR2VR cost 0, 1 and 15\n\n gcc/config/riscv/predicates.md | 2 +-\n gcc/config/riscv/riscv-v.cc | 2 +\n .../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-2-u8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx-3-u8.c | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary.h | 1 +\n .../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 136 ++++++++++++++++++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c | 15 ++\n .../rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c | 15 ++\n 20 files changed, 212 insertions(+), 1 deletion(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u16.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u32.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u64.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsgtu-run-1-u8.c"}