{"id":2229287,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2229287/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/cover/20260428033230.7777-1-alif.zakuan.yuslaimi@altera.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.1/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260428033230.7777-1-alif.zakuan.yuslaimi@altera.com>","date":"2026-04-28T03:32:27","name":"[v2,0/3] SoCFPGA: Update DDR Support for Gen5/Arria10 in U-Boot","submitter":{"id":90458,"url":"http://patchwork.ozlabs.org/api/1.1/people/90458/?format=json","name":"YUSLAIMI, ALIF ZAKUAN","email":"alif.zakuan.yuslaimi@altera.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/cover/20260428033230.7777-1-alif.zakuan.yuslaimi@altera.com/mbox/","series":[{"id":501756,"url":"http://patchwork.ozlabs.org/api/1.1/series/501756/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=501756","date":"2026-04-28T03:32:27","name":"SoCFPGA: Update DDR Support for Gen5/Arria10 in U-Boot","version":2,"mbox":"http://patchwork.ozlabs.org/series/501756/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2229287/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=SMMp8xzz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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The changes include:\n 1. Update MMU/dcache setup across Gen5/Arria10 using common driver\n 2. Add ECC scrubbing support for Gen5/Arria10\n 3. Add DRAM size checking for Gen5/Arria10\n\nThis patch set has been tested on CycloneV devkit with SDMMC boot and RAM boot (TFTP & ARM DS debugger).\nTested on Arria10 devkit with RAM boot as well\n\nv1->v2:\n--------\n- ECC scrubbing, Gen5 DRAM size checking, and shared dram_bank_mmu_setup() is set as optional via Kconfig and\n defaulted on only for the reference Arria10/CycloneV boards to avoid SPL overflows on size-limited Gen5\n defconfigs.\n\nHistory:\n--------\n[v1]: https://patchwork.ozlabs.org/project/uboot/cover/20251216084623.19589-1-alif.zakuan.yuslaimi@altera.com/\n\nAlif Zakuan Yuslaimi (3):\n arm: socfpga: Consolidate dram_bank_mmu_setup()\n ddr: altera: gen5: Add DRAM size checking\n ddr: socfpga: Add ECC DRAM scrubbing support for Gen5/Arria10\n\n arch/arm/mach-socfpga/Kconfig | 21 +++++++\n arch/arm/mach-socfpga/misc.c | 31 ++++++++++\n arch/arm/mach-socfpga/misc_arria10.c | 26 ---------\n arch/arm/mach-socfpga/spl_a10.c | 4 ++\n arch/arm/mach-socfpga/spl_gen5.c | 17 ++++++\n drivers/ddr/altera/Makefile | 4 +-\n drivers/ddr/altera/sdram_arria10.c | 34 +++++------\n drivers/ddr/altera/sdram_gen5.c | 64 ++++++++++++++++++++-\n drivers/ddr/altera/sdram_soc32.c | 85 ++++++++++++++++++++++++++++\n drivers/ddr/altera/sdram_soc32.h | 15 +++++\n 10 files changed, 252 insertions(+), 49 deletions(-)\n create mode 100644 drivers/ddr/altera/sdram_soc32.c\n create mode 100644 drivers/ddr/altera/sdram_soc32.h"}