{"id":2228899,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2228899/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/cover/20260427132447.118272-1-clamor95@gmail.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.1/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20260427132447.118272-1-clamor95@gmail.com>","date":"2026-04-27T13:24:46","name":"[v2,0/1] clk: tegra: support 48MHz clock for pll_p_out1","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/1.1/people/84146/?format=json","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/cover/20260427132447.118272-1-clamor95@gmail.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/covers/2228899/comments/","headers":{"Return-Path":"\n <linux-tegra+bounces-14003-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=quqNynFJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported\nby kernel and causes BUG() early on. Fix this by adding 48MHz\nclock support for pll_p_out1 along with 48MHz support for pll_a,\nmain pll_p_out1 descendant.\n\n---\nChanges in v2:\n- aligned with downstream 3.4 kernel for tegra114 logic\n---\n\nDmitry Osipenko (1):\n  clk: tegra: support 48MHz clock for pll_p_out1\n\n drivers/clk/tegra/clk-pll.c | 1 +\n 1 file changed, 1 insertion(+)"}