{"id":2228589,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2228589/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260427060849.749179-1-314abh@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260427060849.749179-1-314abh@gmail.com>","date":"2026-04-27T06:08:48","name":"[0/1] target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL","submitter":{"id":93260,"url":"http://patchwork.ozlabs.org/api/1.1/people/93260/?format=json","name":"Abhigyan Kumar","email":"314abh@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260427060849.749179-1-314abh@gmail.com/mbox/","series":[{"id":501577,"url":"http://patchwork.ozlabs.org/api/1.1/series/501577/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501577","date":"2026-04-27T06:08:48","name":"target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL","version":1,"mbox":"http://patchwork.ozlabs.org/series/501577/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2228589/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=darBXUZG;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x52f.google.com","X-Spam_score_int":"-13","X-Spam_score":"-1.4","X-Spam_bar":"-","X-Spam_report":"(-1.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n FROM_STARTS_WITH_NUMS=0.738, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This patch ensures that the read-only zero bit (i.e. the 11th bit) of\nmedeleg remains zero, adhering the RISC-V specification.\n\nI'm a first time contributor. I was a bit confused when it came to\nwriting tests for this. However, I did debug it via gdb myself and\nconfirmed the patch works. I would like to seek guidance on how can I\nadd a test for CSR issues like this -- or if it's even required in this\nspecific case.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3438\n\nAbhigyan Kumar (1):\n target/riscv: Fix medeleg[11] read-only zero bit for M-mode ECALL\n\n target/riscv/csr.c | 5 ++++-\n 1 file changed, 4 insertions(+), 1 deletion(-)"}