{"id":2228148,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2228148/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260425131721.932250-1-joel@jms.id.au/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260425131721.932250-1-joel@jms.id.au>","date":"2026-04-25T13:17:06","name":"[v4,00/13] hw/riscv: Add the Tenstorrent Atlantis machine","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/1.1/people/48628/?format=json","name":"Joel Stanley","email":"joel@jms.id.au"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260425131721.932250-1-joel@jms.id.au/mbox/","series":[{"id":501439,"url":"http://patchwork.ozlabs.org/api/1.1/series/501439/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501439","date":"2026-04-25T13:17:08","name":"hw/riscv: Add the Tenstorrent Atlantis machine","version":4,"mbox":"http://patchwork.ozlabs.org/series/501439/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2228148/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Yv4fQ5yj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g2r6d2kvpz1yHv\n\tfor ; Sat, 25 Apr 2026 23:20:25 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wGctW-0006zA-76; Sat, 25 Apr 2026 09:18:02 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wGctT-0006yM-R9\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:17:59 -0400","from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wGctQ-0008Gl-Nq\n for qemu-devel@nongnu.org; Sat, 25 Apr 2026 09:17:59 -0400","by mail-pf1-x431.google.com with SMTP id\n d2e1a72fcca58-82f33d28c1dso4764824b3a.3\n for ; Sat, 25 Apr 2026 06:17:55 -0700 (PDT)","from donnager-debian.. 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Thanks for the reviews.\n\n - Describe PCIe mappings separately from the MemMapEntry table so\n the mappings aren't mixed with fixed hardware addresses. The\n mappings used are changed too, and the XXX comment and check was\n dropped\n - Move temperature sensor from bus 0 to bus 4 and use ti,tmp105\n compatible instead of national,lm75 to match the QEMU model name \n - Add i2c_get_bus() to do bounds checking on getting i2c buses\n - Make halting payload const \n - Don't remove rootfs in functional test, the test framework handles\n cleanup\n - Rename Svadu patch to to better describe what it does\n - Other minor cleanups\n\nv3: https://lore.kernel.org/qemu-devel/20260421053140.752059-1-joel@jms.id.au/\n\nOriginal cover letter:\n\nIntroducing Tenstorrent Atlantis!\n\n The Tenstorrent Atlantis platform is a collaboration between Tenstorrent\n and CoreLab Technology. It is based on the Atlantis SoC, which includes\n the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.\n\n The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant\n RISC-V CPU.\n\nThis initial series adds the base machine support including:\n\n - AIA (Advanced Interrupt Architecture) support\n - PCIe controller and DesignWare I2C integration\n - Serial console and device tree generation\n - Functional tests for OpenSBI+Linux boot\n\nChris Rauer (1):\n hw/i2c: Add designware i2c controller\n\nJoel Stanley (5):\n hw/riscv/virt: Move AIA initialisation to helper file\n hw/riscv/aia: Provide number of irq sources\n hw/riscv: Add Tenstorrent Atlantis machine\n hw/riscv/atlantis: Integrate i2c buses\n hw/riscv/atlantis: Add some i2c peripherals\n\nNicholas Piggin (7):\n hw/riscv/boot: Describe discontiguous memory in boot_info\n hw/riscv/boot: Account for discontiguous memory when loading firmware\n hw/riscv/boot: Provide a simple halting payload\n target/riscv: tt-ascalon: Enable Zkr extension\n target/riscv: tt-ascalon: Enable Svadu by removing Svade\n hw/riscv/atlantis: Add PCIe controller\n tests/functional/riscv64: Add tt-atlantis tests\n\n MAINTAINERS | 20 +\n docs/system/riscv/tt_atlantis.rst | 38 +\n docs/system/target-riscv.rst | 1 +\n hw/riscv/aia.h | 25 +\n include/hw/i2c/designware_i2c.h | 101 ++\n include/hw/riscv/boot.h | 13 +-\n include/hw/riscv/tt_atlantis.h | 86 ++\n include/hw/riscv/virt.h | 2 +-\n hw/i2c/designware_i2c.c | 817 ++++++++++++++++\n hw/riscv/aia.c | 93 ++\n hw/riscv/boot.c | 45 +-\n hw/riscv/microchip_pfsoc.c | 6 +-\n hw/riscv/opentitan.c | 6 +-\n hw/riscv/shakti_c.c | 6 +-\n hw/riscv/sifive_u.c | 6 +-\n hw/riscv/spike.c | 6 +-\n hw/riscv/tt_atlantis.c | 944 +++++++++++++++++++\n hw/riscv/virt-acpi-build.c | 27 +-\n hw/riscv/virt.c | 96 +-\n hw/riscv/xiangshan_kmh.c | 6 +-\n target/riscv/cpu.c | 2 +-\n hw/i2c/Kconfig | 4 +\n hw/i2c/meson.build | 1 +\n hw/i2c/trace-events | 4 +\n hw/riscv/Kconfig | 19 +\n hw/riscv/meson.build | 3 +-\n tests/functional/riscv64/meson.build | 1 +\n tests/functional/riscv64/test_opensbi.py | 4 +\n tests/functional/riscv64/test_tt_atlantis.py | 59 ++\n 29 files changed, 2333 insertions(+), 108 deletions(-)\n create mode 100644 docs/system/riscv/tt_atlantis.rst\n create mode 100644 hw/riscv/aia.h\n create mode 100644 include/hw/i2c/designware_i2c.h\n create mode 100644 include/hw/riscv/tt_atlantis.h\n create mode 100644 hw/i2c/designware_i2c.c\n create mode 100644 hw/riscv/aia.c\n create mode 100644 hw/riscv/tt_atlantis.c\n create mode 100755 tests/functional/riscv64/test_tt_atlantis.py"}