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helo=mail-pl1-x62f.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"From: Frank Chang \n\nSupport the true Zicclsm extension so that we can trap misaligned accesses\nwhen the extension is disabled.\n\nZicclsm is set to true by default to be backwards compatible with the old\nRISC-V QEMU design.\n\nTo disable Zicclsm, simply set zicclsm=false, e.g.:\n -cpu rv64,zicclsm=false\n\nQEMU will raise a misaligned load/store exception when executing misaligned\nload/store instructions.\n\nFrank Chang (4):\n target/riscv: Add Zicclsm CPU option\n target/riscv: Support raising misaligned exceptions for scalar\n loads/stores\n target/riscv: Support raising misaligned exceptions for vector\n loads/stores\n target/riscv: Expose Zicclsm extension as a CPU property\n\n target/riscv/cpu.c | 4 +-\n target/riscv/cpu_cfg_fields.h.inc | 2 +\n target/riscv/insn_trans/trans_rvi.c.inc | 6 ++\n target/riscv/insn_trans/trans_rvv.c.inc | 3 +-\n target/riscv/vector_helper.c | 82 ++++++++++++++++++++-----\n 5 files changed, 80 insertions(+), 17 deletions(-)\n\n--\n2.43.0"}