{"id":2225059,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2225059/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/cover/20260420104332.153640-1-biju.das.jz@bp.renesas.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.1/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260420104332.153640-1-biju.das.jz@bp.renesas.com>","date":"2026-04-20T10:43:17","name":"[v5,0/9] Add Renesas RZ/G3E GPT support","submitter":{"id":87968,"url":"http://patchwork.ozlabs.org/api/1.1/people/87968/?format=json","name":"Biju","email":"biju.das.au@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/cover/20260420104332.153640-1-biju.das.jz@bp.renesas.com/mbox/","series":[{"id":500593,"url":"http://patchwork.ozlabs.org/api/1.1/series/500593/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=500593","date":"2026-04-20T10:43:17","name":"Add Renesas RZ/G3E GPT support","version":5,"mbox":"http://patchwork.ozlabs.org/series/500593/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2225059/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=dpYPIpNB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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It also has additional clocks\nand resets (bus clock and rst_s).\n\nTo accommodate these differences cleanly the series proceeds as follows:\n\nPatches 1-2 add DT binding documentation for the renesas,poegs property\n(allowing GPT channels to be linked with POEG for output-disable) and\nimplement the corresponding driver support. This configures GTINTAD to\nroute output-disable requests to the correct POEG group and sets GTIOR\nto tri-state both output pins on an output-disable event.\n\nPatch 3 is a small cleanup removing an unused parameter from\nrzg2l_gpt_calculate_prescale().\n\nPatch 4 migrates the driver from the legacy .get_state/.apply ops to\nthe new waveform callback interface, introducing struct\nrzg2l_gpt_waveform to hold the hardware configuration (gtpr, gtccr,\nprescale) for a single channel.\n\nPatches 5-7 introduce struct rzg2l_gpt_info to capture SoC-specific\nhardware differences, adding fields for the GTCR prescaler mask\n(gtcr_tpcs), the prescaler multiplier (prescale_mult), and a\ncalculate_prescale() function pointer. This cleanly abstracts the\nper-SoC prescaler logic needed for RZ/G3E.\n\nPatch 8 adds DT binding documentation for the RZ/G3E GPT\n(renesas,r9a09g047-gpt), covering its 16-channel layout, 64 interrupts,\ndual clocks and dual resets.\n\nPatch 9 adds the RZ/G3E driver support itself, wiring up the new\nrzg3e_data match entry with its own prescale calculation, prescaler\nfield mask, and prescale multiplier.\n\nv4->v5:\n * Merged GPT linking POEG patch series here.\n * Dropped suspend/resume patch; will be added later.\n * Updated commit description for patches #2, #4, #5, and #6.\n * Replaced return type of rzg2l_gpt_poeg_init() from void to int and\n probe() check this return value.\n * Added more error checks in rzg2l_gpt_poeg_init().\n * Added a patch to drop the unused rzg2l_gpt_chip parameter from\n rzg2l_gpt_calculate_prescale().\n * Updated rzg2l_gpt_round_waveform_tohw() to initialize gtccr when the\n period of the second channel is smaller.\n * Replaced period_ticks with RZG2L_MAX_TICKS for the duty_ticks maximum\n value check in rzg2l_gpt_round_waveform_tohw().\nv3->v4:\n * Added wave form callback conversion back to this patch series.\n * Updated rzg2l_gpt_is_ch_enabled() fit into 80-character limit for\n consistency with other functions.\n * Dropped field_{get,prep} as mainline now support it.\n * Updated commit description for patch#3\n * Retained RZG2L_GTCR_TPCS bit definitons\n * Replaced gtcr_tpcs_mask->gtcr_tpcs\n * Updated commit header and description for patch#4\n * Renamed prescale_pow_of_two_mult_factor->prescale_mult\n * Added RZG3E_GTCR_TPCS bit definition for RZ/G3E and added to\n rzg3e_data.\n * Added error checks on suspend() and device set to operational state\n on failure().\n * Added Rb tag from Geert for SoC dtsi.\n * Added SW_GPIO9_CAN1_STB check to gpt0 node.\nv2->v3:\n * Added Rb tag from Rob for bindings patch\n * Dropped wave form callback conversion from this patch series as\n it is covered in another series[1]\n * Added suspend/resume support.\nv1->v2:\n * Created separate document for RZ/G3E GPT.\n * Updated commit header and description for binding patch.\n * Added waveform callback conversion to this series.\n * Collected tag.\n * Added link to hardware manual\n * Updated limitation section in driver patch.\n\nBiju Das (9):\n dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property\n pwm: rzg2l-gpt: Add support for gpt linking with poeg\n pwm: rzg2l-gpt: Drop unused rzg2l_gpt_chip parameter from\n rzg2l_gpt_calculate_prescale()\n pwm: rzg2l-gpt: Convert to waveform callbacks\n pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip\n pwm: rzg2l-gpt: Add prescale_mult variable to struct rzg2l_gpt_info\n pwm: rzg2l-gpt: Add calculate_prescale() callback to struct\n rzg2l_gpt_info\n dt-bindings: pwm: Document RZ/G3E GPT support\n pwm: rzg2l-gpt: Add RZ/G3E support\n\n .../bindings/pwm/renesas,rzg2l-gpt.yaml | 23 ++\n .../bindings/pwm/renesas,rzg3e-gpt.yaml | 323 ++++++++++++++++\n drivers/pwm/pwm-rzg2l-gpt.c | 360 ++++++++++++++----\n 3 files changed, 626 insertions(+), 80 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzg3e-gpt.yaml"}