{"id":2222807,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2222807/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/cover/20260413182456.811543-1-prabhakar.mahadev-lad.rj@bp.renesas.com/","project":{"id":42,"url":"http://patchwork.ozlabs.org/api/1.1/projects/42/?format=json","name":"Linux GPIO development","link_name":"linux-gpio","list_id":"linux-gpio.vger.kernel.org","list_email":"linux-gpio@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260413182456.811543-1-prabhakar.mahadev-lad.rj@bp.renesas.com>","date":"2026-04-13T18:24:50","name":"[v2,0/5] pinctrl: renesas: rzg2l: Fix PM register caching","submitter":{"id":9539,"url":"http://patchwork.ozlabs.org/api/1.1/people/9539/?format=json","name":"Prabhakar","email":"prabhakar.csengg@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-gpio/cover/20260413182456.811543-1-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/","series":[{"id":499739,"url":"http://patchwork.ozlabs.org/api/1.1/series/499739/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499739","date":"2026-04-13T18:24:51","name":"pinctrl: renesas: rzg2l: Fix PM register caching","version":2,"mbox":"http://patchwork.ozlabs.org/series/499739/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2222807/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Y4EDElcR;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; 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The changes include:\n- Fixing SMT register caching to account for the split SMT registers on\n RZ/V2H(P).\n- Adding caching for the SR (Slew Rate) registers during PM suspend/resume.\n- Handling the IOLH configuration for RZ/V2H(P) in the PM cache setup.\n- Adding caching for the NOD (N-ch Open Drain) registers during PM\n suspend/resume.\n- Ensuring that PUPD registers for dedicated pins on RZ/V2H(P) are included\n in the PM cache.\n\nv1->v2:\n- Patches 1, 3, 4, and 5 are new.\n- Patch 2 has been updated to include a dedicated cache for SR registers\n as pointed by sashiko.dev.\n\nCheers,\nPrabhakar\n\nLad Prabhakar (5):\n pinctrl: renesas: rzg2l: Fix SMT register cache handling\n pinctrl: renesas: rzg2l: Add SR register cache for PM suspend/resume\n pinctrl: renesas: rzg2l: Handle RZ/V2H(P) IOLH configuration in PM\n cache\n pinctrl: renesas: rzg2l: Add NOD register cache for PM suspend/resume\n pinctrl: renesas: rzg2l: Handle PUPD for RZ/V2H(P) dedicated pins in\n PM\n\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 113 +++++++++++++++++++++---\n 1 file changed, 102 insertions(+), 11 deletions(-)"}