{"id":2222056,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2222056/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1775843299.git.matheus.bernardino@oss.qualcomm.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"","date":"2026-04-10T17:55:48","name":"[v4,00/16] hexagon: add missing HVX float instructions","submitter":{"id":90606,"url":"http://patchwork.ozlabs.org/api/1.1/people/90606/?format=json","name":"Matheus Tavares Bernardino","email":"matheus.bernardino@oss.qualcomm.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/cover.1775843299.git.matheus.bernardino@oss.qualcomm.com/mbox/","series":[{"id":499491,"url":"http://patchwork.ozlabs.org/api/1.1/series/499491/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499491","date":"2026-04-10T17:55:50","name":"hexagon: add missing HVX float instructions","version":4,"mbox":"http://patchwork.ozlabs.org/series/499491/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2222056/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=BJF3PlvC;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=AevPPDrf;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fsl074S3wz20HT\n\tfor ; Sat, 11 Apr 2026 03:58:15 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wBG5m-0006qC-4x; Fri, 10 Apr 2026 13:56:30 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wBG5Z-0006nL-Pz\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:17 -0400","from mx0a-0031df01.pphosted.com ([205.220.168.131])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wBG5V-0001XS-AA\n for qemu-devel@nongnu.org; Fri, 10 Apr 2026 13:56:17 -0400","from pps.filterd (m0279862.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63AAqj5f1925776\n for ; Fri, 10 Apr 2026 17:56:09 GMT","from mail-dy1-f200.google.com (mail-dy1-f200.google.com\n [74.125.82.200])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4deudjtcf5-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for ; Fri, 10 Apr 2026 17:56:08 +0000 (GMT)","by mail-dy1-f200.google.com with SMTP id\n 5a478bee46e88-2bdd327d970so1344223eec.1\n for ; Fri, 10 Apr 2026 10:56:08 -0700 (PDT)","from hu-mathbern-lv.qualcomm.com (Global_NAT1.qualcomm.com.\n [129.46.96.20]) by smtp.gmail.com with ESMTPSA id\n a92af1059eb24-12c3459f7ffsm4256271c88.3.2026.04.10.10.56.06\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 10 Apr 2026 10:56:06 -0700 (PDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n cc:content-transfer-encoding:date:from:message-id:mime-version\n :subject:to; s=qcppdkim1; bh=z7TUtCBMKK6/GYYlF4XHyWbqgTp4dA//2YP\n 7peowl7U=; b=BJF3PlvCBf1BiCN0b1Av9LE2H3VfIHmf9NTNUMYUuD35aimnIy7\n tE6kq8ZU6irdyTlCyZfZkQO09VTzSfWwqzCr031YtFaHTNrJAQ0ViPggBGFZ9wk/\n ZAeyXQnA6eQxiFTS1kli1bkWBp7qTtWqnKwB3FUPjYYoLa0nqfZk8W/GhcEpXf3l\n 11/jertQaCZitbaXUaXwl8H4bchOqfxcro1o0QkwjhPOHPPMUygu09DKGJPBENkP\n kKLlHN3qMu2yDBy9HbUB6DTix61bFd0Niwguq/PlHUtfJcS2EbUNI0Ogwq8ht2d5\n M0dzXbCCTzXRQ9E3CamhPnFE9LkAll5bgOA==","v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=oss.qualcomm.com; s=google; t=1775843768; x=1776448568; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:from:to:cc:subject:date:message-id:reply-to;\n bh=z7TUtCBMKK6/GYYlF4XHyWbqgTp4dA//2YP7peowl7U=;\n b=AevPPDrfJbe40KezwP+MnsRjvpczhMij/QD2Zjx8mnVpsEpGci4E1LQ4S6ZHRTiyQp\n wkmTClXVPSdDPbfDc9q/Tp2VtvqxUdCkiVevSurd5g3XYOqk+rb7d6G50F1NbMNgFfUa\n 3YDBtqN5RLgcu4JVzUd+oU2Dt78zzenFU1tla+rhsjdoe4eymfl1072k9622zCsJ4oef\n nzsiUZNENDDzsI9bffc6C5h2seS88YuNEawlbYyfoT1ZGhVbbxacZWcpyJSiyvx+bamV\n SGNo+mgVOChZTimIGindFpj5G0jJvSTuGXi5dy9cTpiqP/Fp/WSo4mFWp23jdHdZsXDk\n LLCg=="],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775843768; x=1776448568;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date\n :message-id:reply-to;\n bh=z7TUtCBMKK6/GYYlF4XHyWbqgTp4dA//2YP7peowl7U=;\n b=BYooR610nmeGX4jfcsLlvnHsIVTIO+zd8SOo5LeRoCDgVUzGKny+zu2iE66dIN9Z3n\n 3QxFG5BQcmOgvyzFKGAOtjxietiWmq09zUbK5Qc/4sLhUDNI9RUC6Rf1kmyQRELe7BhQ\n +c1Bq7y4/7lUa2Siw64dQcBfhCD1X6cXJEIz1+ZJuOTKUGR5EShjPWhEwTw7yfFCVpNb\n eUGyI1ePuj6fcS7hT+E6mPmMsXPrCJrUMztjUy/dmMxl4K29AeEx04vp0Xp4mFWhoLF3\n IeTU4gt3YJQSDg4NIFl0olMyId1kO89mIZSxOSNbwixDxW63xhvrULSdBTgL2/0t+Mc5\n s2wg==","X-Gm-Message-State":"AOJu0YxAGzfZ6MB29qGQfAi527641+nzDBxSIm6TYkxigxNLHCspirkt\n 8o7gQcT+TLi8IdwNuQMMX/k4JX+wsWCzDxna2IkSE5WraUXjRV4dQXHjxj/eypbDxYm2JALdZWG\n 2X9DRC7HBZajQy2GOIGmATOvGHbwdJ9yZoVEyCt7CMcJcVTNpyfccjayQ6sW8ZfegiTtM","X-Gm-Gg":"AeBDiev0HVVVoH4kfUVpMZYrmrA9/cn/d8m6mLvh5ZgU/rQ2VNw1ho+9KvjfpOKT5DN\n B/PICDYHtaRW/BpYsrxGp8//1hhmn+KO+8IPIHFemDIoTz83Iw7I0EbnpGJdL+da3bm0S5LXeZ+\n ottaPzVdCJt4qGF53k0z/ES61E+zlC9+HGgdsiGXnHQtSHHT3JaLmFO0idnAOIpqItHRuf/C9vX\n gILvVl6Nfgnwtf8txMmxURvdrgT/gTXODxV72/ipLZ5AcLrWGe3OM/BF6gQ74P1igB8iCcNZlS4\n NJc/xLHq+6+aF8H4xYqWo1K2jc7TN9IOIpzq+YpA/7oO7NMQCwaYAHxprp2mBrVtWuJi1eSceGK\n VW5RP/BMCVSpd8JtKlybIsFzgVruTYWf1l7XrQUoj1A8Yy6YfXNz+6hVwkDvGUKQ25J1OAxPXkI\n BagAbVAwfP","X-Received":["by 2002:a05:7022:ea21:b0:128:f1fd:78be with SMTP id\n a92af1059eb24-12c351acbfemr1712727c88.5.1775843767818;\n Fri, 10 Apr 2026 10:56:07 -0700 (PDT)","by 2002:a05:7022:ea21:b0:128:f1fd:78be with SMTP id\n a92af1059eb24-12c351acbfemr1712705c88.5.1775843766921;\n Fri, 10 Apr 2026 10:56:06 -0700 (PDT)"],"From":"Matheus Tavares Bernardino ","To":"qemu-devel@nongnu.org","Cc":"richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com","Subject":"[PATCH v4 00/16] hexagon: add missing HVX float instructions","Date":"Fri, 10 Apr 2026 10:55:48 -0700","Message-Id":"","X-Mailer":"git-send-email 2.37.2","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Authority-Analysis":"v=2.4 cv=X+hi7mTe c=1 sm=1 tr=0 ts=69d939b8 cx=c_pps\n a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8\n a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=7K7JIuq7Fjm6eQbchdUA:9\n a=6Ab_bkdmUrQuMsNx7PHu:22","X-Proofpoint-GUID":"uXCZRKOgS6PKCmw-swYobfTY4YEVm5gH","X-Proofpoint-ORIG-GUID":"uXCZRKOgS6PKCmw-swYobfTY4YEVm5gH","X-Proofpoint-Spam-Details-Enc":"AW1haW4tMjYwNDEwMDE2OCBTYWx0ZWRfX6wo2TG63Fw/I\n wV7qic/G+nIUVbXlx29teeuVm5It9LIvX+6TSVILswlBDlb9308kZsPk6phG23OoLByh9YwByHW\n XYGxIClOFGFnGbR5Xej6RObEOxlkncyxS0dOTFkyALOiLZO0dg9EELuIdXLGAl1myG4RkkpcUsh\n bjFK8CM09cEOyfk9qdAYncbaSjZNuccFGvO6FHtdoIfG639p8KlkmXcotI8kGYPp+dKIsR/Prv2\n SLG//xKaCYEAejqOe30ZOh9mAHjr1Dn4jjvXzrjim4k0dOyOA/jgtLEUGuTmqem+sZCboo+7naE\n TvlCrUb/DnE41Mxq/qEculB2r7piJeTNm+eJhEmQcQB84BwjkwwI+cH42KDNdAdZ2EhHC+KbNc3\n EFia92aZDMZLbdDvKcpiQfPhAlHl98N2W1gXceWT838rrnN3lNa5FSWvvqqRwSBGJ2E35K5bNDs\n FfwWVsIJubWYEk0yXEg==","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501\n lowpriorityscore=0 suspectscore=0 spamscore=0 bulkscore=0 phishscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100168","Received-SPF":"pass client-ip=205.220.168.131;\n envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com","X-Spam_score_int":"-27","X-Spam_score":"-2.8","X-Spam_bar":"--","X-Spam_report":"(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This patchset adds 59 HVX floating point instructions from Hexagon\nrevisions v68 and v73 that were missing in qemu. Tests are also added at\nthe end.\n\nv3: https://lore.kernel.org/qemu-devel/cover.1775665981.git.matheus.bernardino@oss.qualcomm.com/\nv2: https://lore.kernel.org/qemu-devel/cover.1775122853.git.matheus.bernardino@oss.qualcomm.com/\nv1: https://lore.kernel.org/qemu-devel/cover.1774271525.git.matheus.bernardino@oss.qualcomm.com/\n\nChanges in v4:\n - Renamed bf_to_sf/sf_to_bf helpers to bf16_to_f32/f32_to_bf16 for\n consistency\n - Changed signatures from raw integer types (uint32_t/uint16_t) to the\n proper softfloat typedef types (float32/float16).\n - Fixed vabs_sf, which was incorrectly accessing the .hf vector field\n instead of .sf.\n - Fixed MAX_TESTS_bf\n - Removed unused gen_zero() for Q regs.\n - Added missing hex_test.h dependencies in Makefile.target\n - Added more tests for cmp insns\n\nBrian Cain (1):\n tests/docker: Update hexagon cross toolchain to 22.1.0\n\nMatheus Tavares Bernardino (15):\n target/hexagon: fix incorrect/too-permissive HVX encodings\n target/hexagon/cpu: add HVX IEEE FP extension\n hexagon: group cpu configurations in their own struct\n hexagon: print info on \"-d in_asm\" for disabled IEEE FP instructions\n target/hexagon: add v68 HVX IEEE float arithmetic insns\n target/hexagon: add v68 HVX IEEE float min/max insns\n target/hexagon: add v68 HVX IEEE float misc insns\n target/hexagon: add v68 HVX IEEE float conversion insns\n target/hexagon: add v68 HVX IEEE float compare insns\n target/hexagon: add v73 HVX IEEE bfloat16 insns\n tests/hexagon: add tests for v68 HVX IEEE float arithmetics\n tests/hexagon: add tests for v68 HVX IEEE float min/max\n tests/hexagon: add tests for v68 HVX IEEE float conversions\n tests/hexagon: add tests for v68 HVX IEEE float comparisons\n tests/hexagon: add tests for HVX bfloat\n\n target/hexagon/cpu.h | 10 +-\n target/hexagon/cpu_bits.h | 10 +-\n target/hexagon/mmvec/hvx_ieee_fp.h | 69 ++++\n target/hexagon/mmvec/macros.h | 8 +\n target/hexagon/mmvec/mmvec.h | 3 +\n target/hexagon/printinsn.h | 2 +-\n target/hexagon/translate.h | 1 +\n tests/tcg/hexagon/hex_test.h | 32 ++\n tests/tcg/hexagon/hvx_misc.h | 73 ++++\n target/hexagon/attribs_def.h.inc | 9 +\n disas/hexagon.c | 3 +-\n target/hexagon/arch.c | 8 +\n target/hexagon/cpu.c | 18 +-\n target/hexagon/decode.c | 4 +-\n target/hexagon/mmvec/hvx_ieee_fp.c | 137 +++++++\n target/hexagon/printinsn.c | 7 +-\n target/hexagon/translate.c | 5 +-\n tests/tcg/hexagon/fp_hvx.c | 226 +++++++++++\n tests/tcg/hexagon/fp_hvx_cmp.c | 275 +++++++++++++\n tests/tcg/hexagon/fp_hvx_cvt.c | 219 +++++++++++\n tests/tcg/hexagon/fp_hvx_disabled.c | 57 +++\n target/hexagon/gen_tcg_funcs.py | 11 +\n target/hexagon/hex_common.py | 27 ++\n target/hexagon/imported/mmvec/encode_ext.def | 126 ++++--\n target/hexagon/imported/mmvec/ext.idef | 369 +++++++++++++++++-\n target/hexagon/meson.build | 1 +\n .../dockerfiles/debian-hexagon-cross.docker | 10 +-\n tests/tcg/hexagon/Makefile.target | 14 +\n 28 files changed, 1686 insertions(+), 48 deletions(-)\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.h\n create mode 100644 target/hexagon/mmvec/hvx_ieee_fp.c\n create mode 100644 tests/tcg/hexagon/fp_hvx.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c\n\nRange-diff against v3:\n 1: a04c3c5feb = 1: 1440dd86da tests/docker: Update hexagon cross toolchain to 22.1.0\n 2: c63e568f6c = 2: b9a5a46b82 target/hexagon: fix incorrect/too-permissive HVX encodings\n 3: bd05d9aa88 ! 3: 7889db953a target/hexagon/cpu: add HVX IEEE FP extension\n @@ target/hexagon/hex_common.py: def decl_tcg(self, f, tag, regno):\n def gen_write(self, f, tag):\n f.write(code_fmt(f\"\"\"\\\n gen_vreg_write_pair(ctx, {self.hvx_off()}, {self.reg_num},\n -@@ target/hexagon/hex_common.py: def decl_tcg(self, f, tag, regno):\n - TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n - \"\"\"))\n -+ def gen_zero(self, f):\n -+ f.write(code_fmt(f\"\"\"\\\n -+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n -+ sizeof(MMQReg), sizeof(MMQReg), 0);\n -+ \"\"\"))\n - def gen_write(self, f, tag):\n - pass\n - def helper_hvx_desc(self, f):\n -@@ target/hexagon/hex_common.py: def decl_tcg(self, f, tag, regno):\n - TCGv_ptr {self.reg_tcg()} = tcg_temp_new_ptr();\n - tcg_gen_addi_ptr({self.reg_tcg()}, tcg_env, {self.hvx_off()});\n - \"\"\"))\n -+ def gen_zero(self, f):\n -+ f.write(code_fmt(f\"\"\"\\\n -+ tcg_gen_gvec_dup_imm(MO_64, {self.hvx_off()},\n -+ sizeof(MMQReg), sizeof(MMQReg), 0);\n -+ \"\"\"))\n - def gen_write(self, f, tag):\n - pass\n - def helper_hvx_desc(self, f):\n 4: d7cc954b23 ! 4: ac72a36fd8 hexagon: group cpu configurations in their own struct\n @@ Commit message\n \n This will be used in a follow up commit.\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/cpu.h ##\n 5: 192fd1ca5c ! 5: e24b76d95a hexagon: print info on \"-d in_asm\" for disabled IEEE FP instructions\n @@ Commit message\n \n 0x00020e30: 0x1f82e1c0 { V0.sf = vadd(V1.sf,V2.sf) (disabled: no ieee_fp) }\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/cpu_bits.h ##\n 6: 42b4b2d1c6 ! 6: 8c9ded658c target/hexagon: add v68 HVX IEEE float arithmetic insns\n @@ Commit message\n - vadd_sf_sf, vsub_sf_sf, vadd_sf_hf, vsub_sf_hf: add/sub with sf output\n - vadd_hf_hf, vsub_hf_hf: add/sub with hf output\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/cpu.h ##\n 7: 0104072468 ! 7: a89b231b2c target/hexagon: add v68 HVX IEEE float min/max insns\n @@ Commit message\n The Hexagon qfloat variants are similar to the IEEE-754 ones, but they\n handle NaN slightly differently. See comment on hvx_ieee_fp.h\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/mmvec/hvx_ieee_fp.h ##\n @@ target/hexagon/mmvec/hvx_ieee_fp.h: float32 fp_mult_sf_hf(float16 a1, float16 a2\n float_status *fp_status);\n \n +/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than -INF */\n -+uint32_t qf_max_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n -+uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n -+uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n -+uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n ++float32 qf_max_sf(float32 a1, float32 a2, float_status *fp_status);\n ++float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status);\n ++float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status);\n ++float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status);\n +\n #endif\n \n @@ target/hexagon/mmvec/hvx_ieee_fp.c: float32 fp_vdmpy(float16 a1, float16 a2, flo\n +#define float16_is_pos_nan(X) (float16_is_any_nan(X) && !float16_is_neg(X))\n +#define float16_is_neg_nan(X) (float16_is_any_nan(X) && float16_is_neg(X))\n +\n ++/* Qfloat min/max treat +NaN as greater than +INF and -NaN as smaller than -INF */\n +float32 qf_max_sf(float32 a1, float32 a2, float_status *fp_status)\n +{\n + if (float32_is_pos_nan(a1) || float32_is_neg_nan(a2)) {\n 8: 2aa7f10503 ! 8: 27a5ca1ce3 target/hexagon: add v68 HVX IEEE float misc insns\n @@ Commit message\n - vfneg_hf, vfneg_sf: vector floating-point negate\n - vabs_hf, vabs_sf: vector absolute value\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/imported/mmvec/encode_ext.def ##\n @@ target/hexagon/imported/mmvec/ext.idef: ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,\"\n +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, \"Vd32.hf=vabs(Vu32.hf)\", \\\n + \"Vector IEEE abs: hf\", VdV.hf[i] = float16_abs(VuV.hf[i]))\n +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, \"Vd32.sf=vabs(Vu32.sf)\", \\\n -+ \"Vector IEEE abs: sf\", VdV.hf[i] = float32_abs(VuV.hf[i]))\n ++ \"Vector IEEE abs: sf\", VdV.sf[i] = float32_abs(VuV.sf[i]))\n +\n /******************************************************************************\n DEBUG Vector/Register Printing\n 9: 99bac24648 ! 9: 7fecae322c target/hexagon: add v68 HVX IEEE float conversion insns\n @@ Commit message\n - vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float\n - vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/mmvec/hvx_ieee_fp.h ##\n @@ target/hexagon/mmvec/hvx_ieee_fp.h\n \n float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);\n float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n -@@ target/hexagon/mmvec/hvx_ieee_fp.h: uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n - uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n - uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n +@@ target/hexagon/mmvec/hvx_ieee_fp.h: float32 qf_min_sf(float32 a1, float32 a2, float_status *fp_status);\n + float16 qf_max_hf(float16 a1, float16 a2, float_status *fp_status);\n + float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status);\n \n +int32_t conv_w_sf(float32 a, float_status *fp_status);\n +int16_t conv_h_hf(float16 a, float_status *fp_status);\n @@ target/hexagon/imported/mmvec/ext.idef: ITERATOR_INSN_ANY_SLOT_DOUBLE_VEC(WIDTH,\n EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_CVI_VS_3SRC,A_NOTE_SHIFT_RESOURCE,A_NOTE_NOVP,A_NOTE_VA_UNARY), \\\n @@ target/hexagon/imported/mmvec/ext.idef: ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, \"Vd32.hf=vabs(Vu32.hf)\", \\\n ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, \"Vd32.sf=vabs(Vu32.sf)\", \\\n - \"Vector IEEE abs: sf\", VdV.hf[i] = float32_abs(VuV.hf[i]))\n + \"Vector IEEE abs: sf\", VdV.sf[i] = float32_abs(VuV.sf[i]))\n \n +/* Two pipes: P2 & P3, two outputs, 16-bit */\n +#define ITERATOR_INSN_IEEE_FP_DOUBLE_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n10: 9518dd95bd ! 10: ebc920dfcf target/hexagon: add v68 HVX IEEE float compare insns\n @@ Commit message\n - V6_vgthf_or, V6_vgtsf_or: greater-than with predicate-or\n - V6_vgthf_xor, V6_vgtsf_xor: greater-than with predicate-xor\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/mmvec/hvx_ieee_fp.h ##\n -@@ target/hexagon/mmvec/hvx_ieee_fp.h: uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n +@@ target/hexagon/mmvec/hvx_ieee_fp.h: float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status);\n int32_t conv_w_sf(float32 a, float_status *fp_status);\n int16_t conv_h_hf(float16 a, float_status *fp_status);\n \n +/* IEEE - FP compare instructions */\n -+uint32_t cmpgt_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n -+uint16_t cmpgt_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n ++uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status);\n ++uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status);\n +\n #endif\n \n11: f84d180547 ! 11: d408ee2b2c target/hexagon: add v73 HVX IEEE bfloat16 insns\n @@ Commit message\n Conversion operations:\n - V6_vcvt_bf_sf: convert sf to bf16\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## target/hexagon/mmvec/hvx_ieee_fp.h ##\n @@ target/hexagon/mmvec/hvx_ieee_fp.h\n +\n #define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status)\n #define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status)\n -+#define bf_to_sf(A) bfloat16_to_float32(A, &env->hvx_fp_status)\n ++#define bf16_to_f32(A) bfloat16_to_float32(A, &env->hvx_fp_status)\n \n float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);\n float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n @@ target/hexagon/mmvec/hvx_ieee_fp.h: int16_t conv_h_hf(float16 a, float_status *fp_status);\n - uint32_t cmpgt_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n - uint16_t cmpgt_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n + uint32_t cmpgt_sf(float32 a1, float32 a2, float_status *fp_status);\n + uint16_t cmpgt_hf(float16 a1, float16 a2, float_status *fp_status);\n \n +/* IEEE BFloat instructions */\n +\n +#define fp_mult_sf_bf(A, B) \\\n -+ float32_mul(bf_to_sf(A), bf_to_sf(B), &env->hvx_fp_status)\n ++ float32_mul(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n +\n +#define fp_add_sf_bf(A, B) \\\n -+ float32_add(bf_to_sf(A), bf_to_sf(B), &env->hvx_fp_status)\n ++ float32_add(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n +\n +#define fp_sub_sf_bf(A, B) \\\n -+ float32_sub(bf_to_sf(A), bf_to_sf(B), &env->hvx_fp_status)\n ++ float32_sub(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status)\n +\n +#define fp_mult_sf_bf_acc(f1, f2, f3) \\\n -+ float32_muladd(bf_to_sf(f1), bf_to_sf(f2), f3, 0, &env->hvx_fp_status)\n ++ float32_muladd(bf16_to_f32(f1), bf16_to_f32(f2), f3, 0, &env->hvx_fp_status)\n +\n -+static inline uint16_t sf_to_bf(int32_t A, float_status *fp_status)\n ++static inline bfloat16 f32_to_bf16(float32 A, float_status *fp_status)\n +{\n + uint32_t rslt = A;\n + if ((rslt & 0x1FFFF) == 0x08000) {\n @@ target/hexagon/mmvec/hvx_ieee_fp.h: int16_t conv_h_hf(float16 a, float_status *f\n +}\n +\n +#define fp_min_bf(A, B) \\\n -+ sf_to_bf(float32_min(bf_to_sf(A), bf_to_sf(B), &env->hvx_fp_status), \\\n ++ f32_to_bf16(float32_min(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status), \\\n + &env->hvx_fp_status);\n +\n +#define fp_max_bf(A, B) \\\n -+ sf_to_bf(float32_max(bf_to_sf(A), bf_to_sf(B), &env->hvx_fp_status), \\\n ++ f32_to_bf16(float32_max(bf16_to_f32(A), bf16_to_f32(B), &env->hvx_fp_status), \\\n + &env->hvx_fp_status);\n +\n #endif\n @@ target/hexagon/imported/mmvec/ext.idef: ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h\n + fCVI_VX_NO_TMP_LD(); fBFLOAT())\n +ITERATOR_INSN_IEEE_FP_16(32, vcvt_bf_sf,\n + \"Vd32.bf=vcvt(Vu32.sf,Vv32.sf)\", \"Vector IEEE cvt: sf to bf\",\n -+ VdV.bf[2*i] = sf_to_bf(VuV.sf[i], &env->hvx_fp_status);\n -+ VdV.bf[2*i+1] = sf_to_bf(VvV.sf[i], &env->hvx_fp_status); fBFLOAT())\n ++ VdV.bf[2*i] = f32_to_bf16(VuV.sf[i], &env->hvx_fp_status);\n ++ VdV.bf[2*i+1] = f32_to_bf16(VvV.sf[i], &env->hvx_fp_status); fBFLOAT())\n +\n +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vmax_bf, \"Vd32.bf=vmax(Vu32.bf,Vv32.bf)\",\n + \"Vector IEEE max: bf\", VdV.bf[i] = fp_max_bf(VuV.bf[i], VvV.bf[i]);\n12: e66f33dc97 ! 12: cde613d444 tests/hexagon: add tests for v68 HVX IEEE float arithmetics\n @@ Metadata\n ## Commit message ##\n tests/hexagon: add tests for v68 HVX IEEE float arithmetics\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## tests/tcg/hexagon/hex_test.h ##\n @@ tests/tcg/hexagon/fp_hvx.c (new)\n +\n +static void test_new(void)\n +{\n -+ asm volatile(\"r0 = #0x2\\n\"\n ++ asm volatile(\"r0 = #%2\\n\"\n + \"v0 = vsplat(r0)\\n\"\n + \"vmem(%1 + #0) = v0\\n\"\n -+ \"r1 = #0x1\\n\"\n ++ \"r1 = #%3\\n\"\n + \"v1 = vsplat(r1)\\n\"\n + \"v2 = vsplat(r1)\\n\"\n + \"{\\n\"\n @@ tests/tcg/hexagon/fp_hvx.c (new)\n + \" vmem(%0 + #0) = v0.new\\n\"\n + \"}\\n\"\n + :\n -+ : \"r\"(output), \"r\"(expect)\n ++ : \"r\"(output), \"r\"(expect), \"i\"(SF_two), \"i\"(SF_one)\n + : \"r0\", \"r1\", \"v0\", \"v1\", \"v2\", \"memory\");\n + check_output_w(__LINE__, 1);\n +}\n @@ tests/tcg/hexagon/Makefile.target: v68_hvx: CFLAGS += -mhvx -Wno-unused-function\n v69_hvx: v69_hvx.c hvx_misc.h\n v69_hvx: CFLAGS += -mhvx -Wno-unused-function\n v73_scalar: CFLAGS += -Wno-unused-function\n -+fp_hvx: fp_hvx.c hvx_misc.h\n ++fp_hvx: fp_hvx.c hvx_misc.h hex_test.h\n +fp_hvx: CFLAGS += -mhvx -mhvx-ieee-fp\n -+fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h\n ++fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h\n +fp_hvx_disabled: CFLAGS += -mhvx -mhvx-ieee-fp\n +\n +run-fp_hvx_disabled: QEMU_OPTS += -cpu v73,ieee-fp=false\n13: 5055daa72b = 13: 08abae5ee5 tests/hexagon: add tests for v68 HVX IEEE float min/max\n14: 102a431804 ! 14: c20a21aad6 tests/hexagon: add tests for v68 HVX IEEE float conversions\n @@ tests/tcg/hexagon/Makefile.target: HEX_TESTS += scatter_gather\n HEX_TESTS += fp_hvx_disabled\n HEX_TESTS += invalid-slots\n HEX_TESTS += invalid-encoding\n -@@ tests/tcg/hexagon/Makefile.target: fp_hvx: fp_hvx.c hvx_misc.h\n +@@ tests/tcg/hexagon/Makefile.target: fp_hvx: fp_hvx.c hvx_misc.h hex_test.h\n fp_hvx: CFLAGS += -mhvx -mhvx-ieee-fp\n - fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h\n + fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h\n fp_hvx_disabled: CFLAGS += -mhvx -mhvx-ieee-fp\n +fp_hvx_cvt: fp_hvx_cvt.c hvx_misc.h hex_test.h\n +fp_hvx_cvt: CFLAGS += -mhvx -mhvx-ieee-fp\n15: a76a9a239b ! 15: 6b473acaf5 tests/hexagon: add tests for v68 HVX IEEE float comparisons\n @@ Metadata\n ## Commit message ##\n tests/hexagon: add tests for v68 HVX IEEE float comparisons\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## tests/tcg/hexagon/hex_test.h ##\n @@ tests/tcg/hexagon/fp_hvx_cmp.c (new)\n + CHECK(hf, 2);\n +}\n +\n ++static void check_byte_pred(HVX_VectorPred pred, int byte_idx, uint8_t exp_mask,\n ++ int line)\n ++{\n ++ /*\n ++ * Note: ((uint8_t *)&pred)[N] returns the expanded value of bit N:\n ++ * 0xFF if bit is set, 0x00 if clear.\n ++ */\n ++ for (int i = 0; i < 8; i++) {\n ++ int idx = byte_idx * 8 + i;\n ++ int val = ((uint8_t *)&pred)[idx];\n ++ int exp = (exp_mask >> i) & 1 ? 0xff : 0x00;\n ++ if (exp != val) {\n ++ printf(\"ERROR line %d: pred bit %d is 0x%x, should be 0x%x\\n\",\n ++ line, idx, val, exp);\n ++ err++;\n ++ }\n ++ }\n ++}\n ++\n ++#define CHECK_BYTE_PRED(PRED, BYTE, EXP) check_byte_pred(PRED, BYTE, EXP, __LINE__)\n ++\n +static void test_cmp_variants(void)\n +{\n -+ HVX_VectorPred true_pred, false_pred, pred;\n -+ memset(&true_pred, 0xff, sizeof(true_pred));\n -+ memset(&false_pred, 0, sizeof(false_pred));\n ++ HVX_VectorPred pred;\n +\n ++ /*\n ++ * Setup: comparison result will have bits 4-7 set (0xF0 in pred byte 0)\n ++ * - sf[0]: SF_zero > SF_one = false -> bits 0-3 = 0\n ++ * - sf[1]: SF_one > SF_zero = true -> bits 4-7 = 1\n ++ */\n + PREP_TEST();\n -+ ADD_TEST_CMP(sf, SF_one, SF_zero, true);\n + ADD_TEST_CMP(sf, SF_zero, SF_one, false);\n + ADD_TEST_CMP(sf, SF_one, SF_zero, true);\n -+ ADD_TEST_CMP(sf, SF_zero, SF_one, false);\n +\n -+ /* greater and */\n -+ pred = Q6_Q_vcmp_gtand_QVsfVsf(true_pred, buffers[0], buffers[1]);\n -+ *hvx_output = Q6_V_vmux_QVV(pred, true_vec, false_vec);\n -+ for (int j = 0; j < 4; j++) {\n -+ int exp = j % 2 ? 0 : 0xffffffff;\n -+ if (output[0].sf[j] != exp) {\n -+ printf(\"ERROR line %d: gtand %d: expected 0x%x got 0x%x\\n\",\n -+ __LINE__, j, exp, output[0].sf[j]);\n -+ err++;\n -+ }\n -+ }\n -+ pred = Q6_Q_vcmp_gtand_QVsfVsf(false_pred, buffers[0], buffers[1]);\n -+ *hvx_output = Q6_V_vmux_QVV(pred, true_vec, false_vec);\n -+ for (int j = 0; j < 4; j++) {\n -+ if (output[0].sf[j]) {\n -+ printf(\"ERROR line %d: gtand %d: expected false\\n\", __LINE__, j);\n -+ err++;\n -+ }\n -+ }\n ++ /* greater and: 0xF0 & 0xF0 = 0xF0 */\n ++ memset(&pred, 0xF0, sizeof(pred));\n ++ pred = Q6_Q_vcmp_gtand_QVsfVsf(pred, buffers[0], buffers[1]);\n ++ CHECK_BYTE_PRED(pred, 0, 0xF0);\n +\n -+ /* greater or */\n -+ pred = Q6_Q_vcmp_gtor_QVsfVsf(false_pred, buffers[0], buffers[1]);\n -+ *hvx_output = Q6_V_vmux_QVV(pred, true_vec, false_vec);\n -+ for (int j = 0; j < 4; j++) {\n -+ int exp = j % 2 ? 0 : 0xffffffff;\n -+ if (output[0].sf[j] != exp) {\n -+ printf(\"ERROR line %d: gtor %d: expected 0x%x got 0x%x\\n\",\n -+ __LINE__, j, exp, output[0].sf[j]);\n -+ err++;\n -+ }\n -+ }\n -+ pred = Q6_Q_vcmp_gtor_QVsfVsf(true_pred, buffers[0], buffers[1]);\n -+ *hvx_output = Q6_V_vmux_QVV(pred, true_vec, false_vec);\n -+ for (int j = 0; j < 4; j++) {\n -+ if (!output[0].sf[j]) {\n -+ printf(\"ERROR line %d: gtor %d: expected true\\n\", __LINE__, j);\n -+ err++;\n -+ }\n -+ }\n ++ /* greater or: 0x0F | 0xF0 = 0xFF */\n ++ memset(&pred, 0x0F, sizeof(pred));\n ++ pred = Q6_Q_vcmp_gtor_QVsfVsf(pred, buffers[0], buffers[1]);\n ++ CHECK_BYTE_PRED(pred, 0, 0xFF);\n ++\n ++ /* greater xor: 0xFF ^ 0xF0 = 0x0F */\n ++ memset(&pred, 0xFF, sizeof(pred));\n ++ pred = Q6_Q_vcmp_gtxacc_QVsfVsf(pred, buffers[0], buffers[1]);\n ++ CHECK_BYTE_PRED(pred, 0, 0x0F);\n +}\n +\n +int main(void)\n @@ tests/tcg/hexagon/Makefile.target: HEX_TESTS += hvx_misc\n HEX_TESTS += fp_hvx_disabled\n HEX_TESTS += invalid-slots\n HEX_TESTS += invalid-encoding\n -@@ tests/tcg/hexagon/Makefile.target: fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h\n +@@ tests/tcg/hexagon/Makefile.target: fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h hex_test.h\n fp_hvx_disabled: CFLAGS += -mhvx -mhvx-ieee-fp\n fp_hvx_cvt: fp_hvx_cvt.c hvx_misc.h hex_test.h\n fp_hvx_cvt: CFLAGS += -mhvx -mhvx-ieee-fp\n -+fp_hvx_cmp: fp_hvx_cmp.c hvx_misc.h\n ++fp_hvx_cmp: fp_hvx_cmp.c hvx_misc.h hex_test.h\n +fp_hvx_cmp: CFLAGS += -mhvx -mhvx-ieee-fp\n \n run-fp_hvx_disabled: QEMU_OPTS += -cpu v73,ieee-fp=false\n16: 456b1863af ! 16: 10ebb63b81 tests/hexagon: add tests for HVX bfloat\n @@ Metadata\n ## Commit message ##\n tests/hexagon: add tests for HVX bfloat\n \n + Reviewed-by: Taylor Simpson \n Signed-off-by: Matheus Tavares Bernardino \n \n ## tests/tcg/hexagon/hex_test.h ##\n @@ tests/tcg/hexagon/fp_hvx_cmp.c: int err;\n \n #define MAX_TESTS_hf (MAX_VEC_SIZE_BYTES / 2)\n #define MAX_TESTS_sf (MAX_VEC_SIZE_BYTES / 4)\n -+#define MAX_TESTS_bf (MAX_VEC_SIZE_BYTES / 4)\n ++#define MAX_TESTS_bf (MAX_VEC_SIZE_BYTES / 2)\n \n #define TRUE_MASK_sf 0xffffffff\n #define TRUE_MASK_hf 0xffff\n @@ tests/tcg/hexagon/fp_hvx_cmp.c: static void test_cmp_hf(void)\n CHECK(hf, 2);\n }\n \n -+\n +static void test_cmp_bf(void)\n +{\n + /*\n @@ tests/tcg/hexagon/fp_hvx_cmp.c: static void test_cmp_hf(void)\n + CHECK(bf, 2);\n +}\n +\n - static void test_cmp_variants(void)\n + static void check_byte_pred(HVX_VectorPred pred, int byte_idx, uint8_t exp_mask,\n + int line)\n {\n - HVX_VectorPred true_pred, false_pred, pred;\n @@ tests/tcg/hexagon/fp_hvx_cmp.c: int main(void)\n \n test_cmp_sf();"}