{"id":2221123,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2221123/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260408140635.42546-1-zhiwei_liu@linux.alibaba.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.1/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","date":"2026-04-08T14:06:29","name":"[v5,0/6] target/riscv: Implement Smsdid and Smmpt extension","submitter":{"id":84720,"url":"http://patchwork.ozlabs.org/api/1.1/people/84720/?format=json","name":"LIU Zhiwei","email":"zhiwei_liu@linux.alibaba.com"},"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/20260408140635.42546-1-zhiwei_liu@linux.alibaba.com/mbox/","series":[{"id":499183,"url":"http://patchwork.ozlabs.org/api/1.1/series/499183/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499183","date":"2026-04-08T14:06:34","name":"target/riscv: Implement Smsdid and Smmpt extension","version":5,"mbox":"http://patchwork.ozlabs.org/series/499183/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2221123/comments/","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=linux.alibaba.com header.i=@linux.alibaba.com\n header.a=rsa-sha256 header.s=default header.b=VbrrHQ7O;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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a=rsa-sha256; c=relaxed/relaxed;\n d=linux.alibaba.com; s=default;\n t=1775657203; h=From:To:Subject:Date:Message-Id:MIME-Version;\n bh=vFg92j2gZ9NSCF4Z3rmDUVqAYz3+1RHvZHtl0F7a700=;\n b=VbrrHQ7O0+tBHYaVFcF0C2v2YA0EJM5PaonSUmjWzF938XUwrrKlhwgsvNjnnXbrbDZ0ruCesHeGZRsBw9R3CsJ4C8OBw34fy6jAOYIg6wB3iUn5NMjI+f/h7tAEE0jhj7rTQdRf1oB0lge42/+6yXCb+syfrLmtceIwKuK7Vkc=","X-Alimail-AntiSpam":"AC=PASS; BC=-1|-1; BR=01201311R201e4; CH=green;\n DM=||false|;\n DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=maildocker-contentspam033045133197;\n MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=8; SR=0;\n TI=SMTPD_---0X0f.zGJ_1775657201;","From":"LIU Zhiwei ","To":"qemu-devel@nongnu.org","Cc":"qemu-riscv@nongnu.org, chao.liu.zevorn@gmail.com, palmer@dabbelt.com,\n alistair23@gmail.com, daniel.barboza@oss.qualcomm.com, liwei1518@gmail.com,\n LIU Zhiwei ","Subject":"[PATCH v5 0/6] target/riscv: Implement Smsdid and Smmpt extension","Date":"Wed, 8 Apr 2026 22:06:29 +0800","Message-Id":"<20260408140635.42546-1-zhiwei_liu@linux.alibaba.com>","X-Mailer":"git-send-email 2.39.3 (Apple Git-146)","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=115.124.30.124;\n envelope-from=zhiwei_liu@linux.alibaba.com;\n helo=out30-124.freemail.mail.aliyun.com","X-Spam_score_int":"-174","X-Spam_score":"-17.5","X-Spam_bar":"-----------------","X-Spam_report":"(-17.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001,\n USER_IN_DEF_DKIM_WL=-7.5,\n USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"This patch set introduces support for the RISC-V Smmpt (Supervisor\nMemory-tracking and Protection Table) extension. Smmpt provides a\nhardware mechanism for fine-grained memory protection, checked after\naddress translation, which is particularly useful for supervisor-level\nsandboxing and security monitoring.\n\nThe rfc patch set:\nhttps://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html\n\nv4->v5:\n 1. Rebase to master. \nv3->v4:\n 1. Add missing review tags.\nv2->v3:\n 1. Fix build error in patch 2.\n 2. Rebase to master.\n\nrfc->v2:\n 1. When ext_smmpt is false or BARE mode, make other fields in mmpt\n CSR zero.\n 2. Add patch 5 to fix smrnmi ISA string order.\n 3. Fix patch 6 smmpt and smsdid ISA string order.\n 4. Make smmpt and smsdid experiment extensions.\n 5. Add review tags.\n\n\nLIU Zhiwei (6):\n target/riscv: Add basic definitions and CSRs for SMMPT\n target/riscv: Implement core SMMPT lookup logic\n target/riscv: Integrate SMMPT checks into MMU and TLB fill\n target/riscv: Implement SMMPT fence instructions\n target/riscv: Fix smrnmi isa alphabetical order\n target/riscv: Enable SMMPT extension\n\n target/riscv/cpu.c | 6 +-\n target/riscv/cpu.h | 9 +-\n target/riscv/cpu_bits.h | 27 ++\n target/riscv/cpu_cfg_fields.h.inc | 2 +\n target/riscv/cpu_helper.c | 81 +++++-\n target/riscv/csr.c | 95 ++++++\n target/riscv/insn32.decode | 2 +\n .../riscv/insn_trans/trans_privileged.c.inc | 30 ++\n target/riscv/meson.build | 1 +\n target/riscv/pmp.h | 3 +\n target/riscv/riscv_smmpt.c | 274 ++++++++++++++++++\n target/riscv/riscv_smmpt.h | 36 +++\n 12 files changed, 560 insertions(+), 6 deletions(-)\n create mode 100644 target/riscv/riscv_smmpt.c\n create mode 100644 target/riscv/riscv_smmpt.h"}