{"id":2220871,"url":"http://patchwork.ozlabs.org/api/1.1/covers/2220871/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/cover/20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com/","project":{"id":38,"url":"http://patchwork.ozlabs.org/api/1.1/projects/38/?format=json","name":"Linux PWM development","link_name":"linux-pwm","list_id":"linux-pwm.vger.kernel.org","list_email":"linux-pwm@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com>","date":"2026-04-08T10:07:31","name":"[v2,0/2] pwm: clk-pwm: Add GPIO support for constant output levels","submitter":{"id":90715,"url":"http://patchwork.ozlabs.org/api/1.1/people/90715/?format=json","name":"Xilin Wu","email":"sophon@radxa.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-pwm/cover/20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com/mbox/","series":[{"id":499115,"url":"http://patchwork.ozlabs.org/api/1.1/series/499115/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-pwm/list/?series=499115","date":"2026-04-08T10:07:31","name":"pwm: clk-pwm: Add GPIO support for constant output levels","version":2,"mbox":"http://patchwork.ozlabs.org/series/499115/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/covers/2220871/comments/","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pwm@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-pwm+bounces-8518-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=54.204.34.130","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=radxa.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=radxa.com"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frJxF2CTzz1xtJ\n\tfor ; Wed, 08 Apr 2026 20:20:49 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 232B4308B0F3\n\tfor ; Wed, 8 Apr 2026 10:09:18 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 0D0A537CD4B;\n\tWed, 8 Apr 2026 10:08:22 +0000 (UTC)","from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 333E337CD37;\n\tWed, 8 Apr 2026 10:08:11 +0000 (UTC)","from [192.168.30.32] ( [116.234.85.158])\n\tby bizesmtp.qq.com (ESMTP) with\n\tid ; Wed, 08 Apr 2026 18:07:37 +0800 (CST)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775642901; cv=none;\n b=pmfoY+O7kXnU1u8tXP6XdddMTq+0ZYapJTGFXHs8XAFmSYTmE8ia5kKaS6YzHqcfuCHj/iOIdblYAIX8ll+hJuVS1Va5HpxtV4P/Ab/3JPfp5eu3Xevf1CkeLqWO+z7jieFt9O8QsJ4a6LwhD9B98RTPHjLhVPHsS+Ifr6p2HAU=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775642901; c=relaxed/simple;\n\tbh=62ZMMJhiRf3W0pHXfgF2lD/YodlaB0xcTZ2T1wCDpPE=;\n\th=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc;\n b=cAoctGWQXDoJ8HhqVyrdy66Dy8faLysu4hvQ3MdBHzoFWLc7bHDtqNHu2RJ8KfQcC6RjNQ6zpf/a34p3xBEjasitNdvpsal/HF2ca5u3D2p/UfVsExrKZpoMn+40LkIefilTp1O7aCjzRPAjX0mXZuXJvY6Yespm38Yo+CyVAI4=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=radxa.com;\n spf=pass smtp.mailfrom=radxa.com; arc=none smtp.client-ip=54.204.34.130","X-QQ-mid":"zesmtpsz5t1775642864t5fdd2343","X-QQ-Originating-IP":"OPiFM+vDY32D3qaMXmjBX7aGz7F+ikzsRR0LCjXRzZ4=","X-QQ-SSF":"0000000000000000000000000000000","X-QQ-GoodBg":"0","X-BIZMAIL-ID":"1243427011650988679","EX-QQ-RecipientCnt":"10","From":"Xilin Wu ","Subject":"[PATCH v2 0/2] pwm: clk-pwm: Add GPIO support for constant output\n levels","Date":"Wed, 08 Apr 2026 18:07:31 +0800","Message-Id":"<20260408-clk-pwm-gpio-v2-0-d22f1f3498a0@radxa.com>","Precedence":"bulk","X-Mailing-List":"linux-pwm@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-B4-Tracking":"v=1; b=H4sIAAAAAAAC/3WNQQ6CMBBFr0Jm7ZihICIr72FYlNLCqFDSImJI7\n y7g2uVL3n9/Aa8daw9FtIDTE3u2/QriEIFqZd9o5HplECQySilD9Xzg8O6wGdji2WRJleQXyuU\n J1sngtOF5z93KH/tXdddq3Bqb0bIfrfvsf1O8eX/SU4yEKdXCJFKQNObqZD3Lo7IdlCGELzmsB\n De6AAAA","X-Change-ID":"20260406-clk-pwm-gpio-7f63b38908a5","To":"=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= ,\n Rob Herring , Krzysztof Kozlowski ,\n Conor Dooley , Nikita Travkin ","Cc":"linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n Xilin Wu ","X-Mailer":"b4 0.15.1","X-Developer-Signature":"v=1; a=openpgp-sha256; l=1597; i=sophon@radxa.com;\n h=from:subject:message-id; bh=62ZMMJhiRf3W0pHXfgF2lD/YodlaB0xcTZ2T1wCDpPE=;\n b=owGbwMvMwCVmdFg0fe08Iz/G02pJDJnXNF5e6jvRyObbf2pR3ryLIhekzkV83jXln9CbNQInV\n N8dvh57pKOUhUGMi0FWTJFFIZ5hLntl7rWnYqV6MHNYmUCGMHBxCsBE5LIYGVY3ZgYHG0qKnJm1\n cOu5Ze2vPkkLWOo5/VDZm22cm28p/5uR4an00/VBpYy8k7bZmWj+mabJNfXhXoMkWaUTu+VdLyh\n rMQIA","X-Developer-Key":"i=sophon@radxa.com; a=openpgp;\n fpr=205F009D07796DD6E516752E32C31567AD9E324E","X-QQ-SENDSIZE":"520","Feedback-ID":"zesmtpsz:radxa.com:qybglogicsvrsz:qybglogicsvrsz3b-0","X-QQ-XMAILINFO":"MyeHZuBXrvHmp1aiJyB2dH8YhNIfcOptw9xZb7F1qcN8fp1YZKcVjbv0\n\tCOmGHklgHwiBo0bQiWV+AZpkeNgBSgkPz6Ts2kQPucNQ8oCcT7Z6hqrMwANNM9Lff+fKPgT\n\th2X1n8vtGdyU6qgVO/5ClluN0e3nAQfsVmk4CPkG6tVDoQJjzK21z70cF2qIUS7cmiAdFx7\n\tq7VUsknzKxNzOKpdMQgn3wQPbL8q3Vj/Zd7rSwWRsB+C0hREe84XBAVeRaDxe11KN8dcqRM\n\txfyh7LOelh6VbkAM6MbyfEJy31YBI/I685lxIyqD+1CFYzlcW/NhdQ18sPyFWpRoD/J3rNM\n\tCTRgy46eTOND5h/GCd2v0fP/D9Wh38qcV3ktmws1s2850aVpWthu4v2KP2Zvpo/1sS5efWZ\n\tja1AcoVDvDX9a2bDyTDzpyyTWnFd++PS7tVFV2TH1DePZMEOmsAPB1ubtFnfRA9I9rpY+uE\n\tJ2732sL35xPjOGbQN3oDg3QFGP4ZBKCIVgkHm+n2VQvWwskekirVRQH1hVjUv0CBPHVsPiE\n\t+RFH7Cc12vuaaP0SWYavMb9fUCqQYkKRwVt3AVl8JkBKfFlNJOy5VqVJccKbvUYOU3umn2p\n\txDmLEAGs3dXmYGdThhml1aYiybpDf7VObQ/CF7ln6AcSo8SyeTLjA46d4ET5JC5CJN3Hxdw\n\tl6xB9XAO9NSFJzdpBFHu5iI0utVqBKxWZgfcejrsArpzVqVmY0QdgpR4qHZb1p7NP3p3opb\n\tpZASSC9Ilgu+BPTF+e/Zv8yhDNKrlMyuaHXc5A8OuzTESRjo47Za8B24MP5Rvb1bBpA1g9Z\n\t2wx9hT7jQ22WjCmkSI50R7fcpccXWFlY1zMX2ONGyY85sbcoTeaR3KR2FJtJm/H9K7cN05M\n\ty9sZh05hIVtHC0P8l/mx+p4+M6sbP5jr0LCMf1WIAmcgK2K9G1j/ko97h3FKCNQtWDRDp5M\n\tjtFG6iEiWhuKTexZGLiCaTBYHRNuiDD823Bcp9HLW/XKEHvQX8XCojtEJm+b/M7x7VLQu5c\n\tjJttraH9l8UQeKJitwzlweRg/rOuADeS9yv7ihmtIkhRVP5zixT5/mxxjonn9bqsF8tmJOk\n\tPN6/GWMF53BeY5AblrpMt8=","X-QQ-XMRINFO":"NyFYKkN4Ny6FuXrnB5Ye7Aabb3ujjtK+gg==","X-QQ-RECHKSPAM":"0"},"content":"The clk-pwm driver uses a clock with duty cycle control to generate\nPWM output. However, when the PWM is disabled or a 0%/100% duty cycle\nis requested, the clock must be stopped, and the resulting pin level\nis undefined and hardware-dependent.\n\nThis series adds optional GPIO and pinctrl support to the clk-pwm\ndriver. When a GPIO and pinctrl states (\"default\" for clock mux,\n\"gpio\" for GPIO mode) are provided in the device tree, the driver\nswitches the pin to GPIO mode and drives a deterministic output level\nfor disabled/0%/100% states. For normal PWM output the pin is switched\nback to its clock function mux. If no GPIO is provided, the driver\nfalls back to the original clock-only behavior.\n\nSigned-off-by: Xilin Wu \n---\nChanges in v2:\n- Restore the original limitation comments\n- Swap the order of pinctrl_select_state and gpiod_direction_output\n- Handle a situation where pinctrl states were found but no GPIO was provided\n- Link to v1: https://patch.msgid.link/20260406-clk-pwm-gpio-v1-0-40d2f3a20aff@radxa.com\n\n---\nXilin Wu (2):\n dt-bindings: pwm: clk-pwm: add optional GPIO and pinctrl properties\n pwm: clk-pwm: add GPIO and pinctrl support for constant output levels\n\n Documentation/devicetree/bindings/pwm/clk-pwm.yaml | 36 +++++++++-\n drivers/pwm/pwm-clk.c | 84 ++++++++++++++++++++--\n 2 files changed, 115 insertions(+), 5 deletions(-)\n---\nbase-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979\nchange-id: 20260406-clk-pwm-gpio-7f63b38908a5\n\nBest regards,\n-- \nXilin Wu "}