{"id":823,"url":"http://patchwork.ozlabs.org/api/1.0/patches/823/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<1222065154-19310-1-git-send-email-jacmet@sunsite.dk>","date":"2008-09-22T06:32:34","name":"[v3] powerpc: gpio driver for mpc8349/8572/8610 and compatible with OF bindings","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":true,"hash":"3539957eb431f10a4d274e1c7f27f67282e6eeeb","submitter":{"id":103,"url":"http://patchwork.ozlabs.org/api/1.0/people/103/?format=json","name":"Peter Korsgaard","email":"jacmet@sunsite.dk"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1222065154-19310-1-git-send-email-jacmet@sunsite.dk/mbox/","series":[],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/823/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from ozlabs.org (localhost [127.0.0.1])\n\tby ozlabs.org (Postfix) with ESMTP id E8FDDDE183\n\tfor ;\n\tMon, 22 Sep 2008 16:32:53 +1000 (EST)","from fg-out-1718.google.com (fg-out-1718.google.com\n\t[72.14.220.152]) by ozlabs.org (Postfix) with ESMTP id 85FAFDDE08\n\tfor ; Mon, 22 Sep 2008 16:32:39 +1000 (EST)","by fg-out-1718.google.com with SMTP id d23so1391502fga.39\n\tfor ; Sun, 21 Sep 2008 23:32:37 -0700 (PDT)","by 10.86.4.2 with SMTP id 2mr4456365fgd.21.1222065157730;\n\tSun, 21 Sep 2008 23:32:37 -0700 (PDT)","from macbook.be.48ers.dk (191.207-78-194.adsl-fix.skynet.be\n\t[194.78.207.191])\n\tby mx.google.com with ESMTPS id 3sm4977909fge.3.2008.09.21.23.32.35\n\t(version=TLSv1/SSLv3 cipher=RC4-MD5);\n\tSun, 21 Sep 2008 23:32:36 -0700 (PDT)","by macbook.be.48ers.dk (Postfix, from userid 1000)\n\tid 7CF2346099B; Mon, 22 Sep 2008 08:32:34 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; \n\th=domainkey-signature:received:received:received:from:to:cc:subject\n\t:date:message-id:x-mailer:sender;\n\tbh=UEaN8aWa1t3RWJoGCwpes9wHZ3BaxMVGs1nvdc0Fh8w=;\n\tb=BO6913CQr66BswLoGZ62cP79eA9Nsm01AQ+uZVSADK/s7ZVBRIuXdVO+gW9QYfG4WX\n\tlq0dioNX+OysFyC6Bxlp1g5SB9FHKLp3jehr2rjp4aswO9j6AF28BFCOH8mQLzW0Ur0V\n\tMwClUQ5OWRaHN8df5aTNIXgguqrIKP9MF6fZY=","DomainKey-Signature":"a=rsa-sha1; c=nofws; d=gmail.com; s=gamma;\n\th=from:to:cc:subject:date:message-id:x-mailer:sender;\n\tb=TV/IYO54S1dCVeExei/ofhH644MlVhp5gKa+AtoWZreoLR8XS+FYWeumbPqJSFWBs0\n\tHcOFNKthRRTXfKGZ0qtMO4MM501VcYM8Yg+P7pPdeZFwSAUFSo5aslqthw4icd8JccC2\n\t02Pi3/rFcMMAhKXaBWdfb+TkLjhDw8QoWWbIU=","From":"Peter Korsgaard ","To":"galak@kernel.crashing.org, avorontsov@ru.mvista.com,\n\tlinuxppc-dev@ozlabs.org","Subject":"[PATCH v3] powerpc: gpio driver for mpc8349/8572/8610 and compatible\n\twith OF bindings","Date":"Mon, 22 Sep 2008 08:32:34 +0200","Message-Id":"<1222065154-19310-1-git-send-email-jacmet@sunsite.dk>","X-Mailer":"git-send-email 1.5.6.3","X-BeenThere":"linuxppc-dev@ozlabs.org","X-Mailman-Version":"2.1.11","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@ozlabs.org"},"content":"Structured similar to the existing QE GPIO support.\n\nSigned-off-by: Peter Korsgaard \n---\n Changes since v2:\n - Clarified documentation as requested by Kumar.\n\n Changes since v1:\n Incorporated feedback from Anton and Kumar:\n - Core is also used on 8572/8610 so s/83xx/8xxx/\n - Use fsl,mpc8572-gpio / fsl,mpc8610-gpio for 85xx/86xx as compatible\n - Use shadowed data register to handle open drain outputs\n - Expandend dts binding doc, use 8347 as example instead of 8349\n - Misc small cleanups\n\n .../powerpc/dts-bindings/fsl/8xxx_gpio.txt | 40 +++++\n arch/powerpc/sysdev/Kconfig | 9 +\n arch/powerpc/sysdev/Makefile | 1 +\n arch/powerpc/sysdev/mpc8xxx_gpio.c | 170 ++++++++++++++++++++\n 4 files changed, 220 insertions(+), 0 deletions(-)\n create mode 100644 Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt\n create mode 100644 arch/powerpc/sysdev/mpc8xxx_gpio.c","diff":"diff --git a/Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt b/Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt\nnew file mode 100644\nindex 0000000..26c29c4\n--- /dev/null\n+++ b/Documentation/powerpc/dts-bindings/fsl/8xxx_gpio.txt\n@@ -0,0 +1,40 @@\n+GPIO controllers on MPC8xxx SoCs\n+\n+This is for the non-QE/CPM/GUTs GPIO controllers as found on\n+8349, 8572, 8610 and compatible.\n+\n+Every GPIO controller node must have #gpio-cells property defined,\n+this information will be used to translate gpio-specifiers.\n+\n+Required properties:\n+- compatible : \"fsl,-gpio\" followed by \"fsl,mpc8349-gpio\" for\n+ 83xx, \"fsl,mpc8572-gpio\" for 85xx and \"fsl,mpc8610-gpio\" for 86xx.\n+- #gpio-cells : Should be two. The first cell is the pin number and the\n+ second cell is used to specify optional parameters (currently unused).\n+ - interrupts : Interrupt mapping for GPIO IRQ (currently unused).\n+ - interrupt-parent : Phandle for the interrupt controller that\n+ services interrupts for this device.\n+- gpio-controller : Marks the port as GPIO controller.\n+\n+Example of gpio-controller nodes for a MPC8347 SoC:\n+\n+\tgpio1: gpio-controller@c00 {\n+\t\t#gpio-cells = <2>;\n+\t\tcompatible = \"fsl,mpc8347-gpio, fsl,mpc8349-gpio\";\n+\t\treg = <0xc00 0x100>;\n+\t\tinterrupts = <74 0x8>;\n+\t\tinterrupt-parent = <&ipic>;\n+\t\tgpio-controller;\n+\t};\n+\n+\tgpio2: gpio-controller@d00 {\n+\t\t#gpio-cells = <2>;\n+\t\tcompatible = \"fsl,mpc8347-gpio, fsl,mpc8349-gpio\";\n+\t\treg = <0xd00 0x100>;\n+\t\tinterrupts = <75 0x8>;\n+\t\tinterrupt-parent = <&ipic>;\n+\t\tgpio-controller;\n+\t};\n+\n+See booting-without-of.txt for details of how to specify GPIO\n+information for devices.\ndiff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig\nindex 72fb35b..a11cc8f 100644\n--- a/arch/powerpc/sysdev/Kconfig\n+++ b/arch/powerpc/sysdev/Kconfig\n@@ -6,3 +6,12 @@ config PPC4xx_PCI_EXPRESS\n \tbool\n \tdepends on PCI && 4xx\n \tdefault n\n+\n+config MPC8xxx_GPIO\n+\tbool \"MPC8xxx GPIO support\"\n+\tdepends on PPC_MPC831x || PPC_MPC834x || PPC_MPC837x || PPC_85xx || PPC_86xx\n+\tselect GENERIC_GPIO\n+\tselect ARCH_REQUIRE_GPIOLIB\n+\thelp\n+\t Say Y here if you're going to use hardware that connects to the\n+\t MPC831x/834x/837x/8572/8610 GPIOs.\ndiff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile\nindex a90054b..e410764 100644\n--- a/arch/powerpc/sysdev/Makefile\n+++ b/arch/powerpc/sysdev/Makefile\n@@ -15,6 +15,7 @@ obj-$(CONFIG_FSL_SOC)\t\t+= fsl_soc.o\n obj-$(CONFIG_FSL_PCI)\t\t+= fsl_pci.o $(fsl-msi-obj-y)\n obj-$(CONFIG_FSL_LBC)\t\t+= fsl_lbc.o\n obj-$(CONFIG_FSL_GTM)\t\t+= fsl_gtm.o\n+obj-$(CONFIG_MPC8xxx_GPIO)\t+= mpc8xxx_gpio.o\n obj-$(CONFIG_RAPIDIO)\t\t+= fsl_rio.o\n obj-$(CONFIG_TSI108_BRIDGE)\t+= tsi108_pci.o tsi108_dev.o\n obj-$(CONFIG_QUICC_ENGINE)\t+= qe_lib/\ndiff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c\nnew file mode 100644\nindex 0000000..3c1f608\n--- /dev/null\n+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c\n@@ -0,0 +1,170 @@\n+/*\n+ * GPIOs on MPC8349/8572/8610 and compatible\n+ *\n+ * Copyright (C) 2008 Peter Korsgaard \n+ *\n+ * This file is licensed under the terms of the GNU General Public License\n+ * version 2. This program is licensed \"as is\" without any warranty of any\n+ * kind, whether express or implied.\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+#define MPC8XXX_GPIO_PINS\t32\n+\n+#define GPIO_DIR\t\t0x00\n+#define GPIO_ODR\t\t0x04\n+#define GPIO_DAT\t\t0x08\n+#define GPIO_IER\t\t0x0c\n+#define GPIO_IMR\t\t0x10\n+#define GPIO_ICR\t\t0x14\n+\n+struct mpc8xxx_gpio_chip {\n+\tstruct of_mm_gpio_chip mm_gc;\n+\tspinlock_t lock;\n+\n+\t/* shadowed data register to be able to clear/set output pins in\n+\t open drain mode safely */\n+\tu32 data;\n+};\n+\n+static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)\n+{\n+\treturn 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);\n+}\n+\n+static inline struct mpc8xxx_gpio_chip *\n+to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)\n+{\n+\treturn container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);\n+}\n+\n+static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)\n+{\n+\tstruct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);\n+\n+\tmpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);\n+}\n+\n+static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)\n+{\n+\tstruct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);\n+\n+\treturn !!(in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio));\n+}\n+\n+static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)\n+{\n+\tstruct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);\n+\tstruct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&mpc8xxx_gc->lock, flags);\n+\n+\tif (val)\n+\t\tmpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);\n+\telse\n+\t\tmpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);\n+\n+\tout_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);\n+\n+\tspin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);\n+}\n+\n+static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)\n+{\n+\tstruct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);\n+\tstruct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&mpc8xxx_gc->lock, flags);\n+\n+\tout_be32(mm->regs + GPIO_DIR,\n+\t\t in_be32(mm->regs + GPIO_DIR) & ~mpc8xxx_gpio2mask(gpio));\n+\n+\tspin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)\n+{\n+\tstruct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);\n+\tstruct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);\n+\tunsigned long flags;\n+\n+\tmpc8xxx_gpio_set(gc, gpio, val);\n+\n+\tspin_lock_irqsave(&mpc8xxx_gc->lock, flags);\n+\tout_be32(mm->regs + GPIO_DIR,\n+\t\t in_be32(mm->regs + GPIO_DIR) | mpc8xxx_gpio2mask(gpio));\n+\n+\tspin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);\n+\n+\treturn 0;\n+}\n+\n+static int __init mpc8xxx_add_controller(struct device_node *np)\n+{\n+\tstruct mpc8xxx_gpio_chip *mpc8xxx_gc;\n+\tstruct of_mm_gpio_chip *mm_gc;\n+\tstruct of_gpio_chip *of_gc;\n+\tstruct gpio_chip *gc;\n+\tint ret;\n+\n+\tmpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);\n+\tif (!mpc8xxx_gc) {\n+\t\tret = -ENOMEM;\n+\t\tgoto err;\n+\t}\n+\n+\tspin_lock_init(&mpc8xxx_gc->lock);\n+\n+\tmm_gc = &mpc8xxx_gc->mm_gc;\n+\tof_gc = &mm_gc->of_gc;\n+\tgc = &of_gc->gc;\n+\n+\tmm_gc->save_regs = mpc8xxx_gpio_save_regs;\n+\tof_gc->gpio_cells = 2;\n+\tgc->ngpio = MPC8XXX_GPIO_PINS;\n+\tgc->direction_input = mpc8xxx_gpio_dir_in;\n+\tgc->direction_output = mpc8xxx_gpio_dir_out;\n+\tgc->get = mpc8xxx_gpio_get;\n+\tgc->set = mpc8xxx_gpio_set;\n+\n+\tret = of_mm_gpiochip_add(np, mm_gc);\n+\tif (ret)\n+\t\tgoto err;\n+\n+\treturn 0;\n+\n+err:\n+\tpr_err(\"%s: registration failed with status %d\\n\",\n+\t np->full_name, ret);\n+\tkfree(mpc8xxx_gc);\n+\n+\treturn ret;\n+}\n+\n+static int __init mpc8xxx_add_gpiochips(void)\n+{\n+\tstruct device_node *np;\n+\n+\tfor_each_compatible_node(np, NULL, \"fsl,mpc8349-gpio\")\n+\t\tmpc8xxx_add_controller(np);\n+\n+\tfor_each_compatible_node(np, NULL, \"fsl,mpc8572-gpio\")\n+\t\tmpc8xxx_add_controller(np);\n+\n+\tfor_each_compatible_node(np, NULL, \"fsl,mpc8610-gpio\")\n+\t\tmpc8xxx_add_controller(np);\n+\n+\treturn 0;\n+}\n+arch_initcall(mpc8xxx_add_gpiochips);\n","prefixes":["v3"]}