{"id":809674,"url":"http://patchwork.ozlabs.org/api/1.0/patches/809674/?format=json","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.0/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20170904130335.23280-2-maxime.ripard@free-electrons.com>","date":"2017-09-04T13:03:34","name":"[v3,1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"c8466caf1c258f00dbee5bf1e00c3e55f78072ea","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/1.0/people/12916/?format=json","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170904130335.23280-2-maxime.ripard@free-electrons.com/mbox/","series":[{"id":1376,"url":"http://patchwork.ozlabs.org/api/1.0/series/1376/?format=json","date":"2017-09-04T13:03:33","name":"media: v4l: Add support for the Cadence MIPI-CSI2 RX","version":3,"mbox":"http://patchwork.ozlabs.org/series/1376/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809674/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xm95Y4nF4z9t2c\n\tfor ;\n\tMon, 4 Sep 2017 23:03:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753654AbdIDNDl (ORCPT\n\t);\n\tMon, 4 Sep 2017 09:03:41 -0400","from mail.free-electrons.com ([62.4.15.54]:42588 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753579AbdIDNDk (ORCPT\n\t); Mon, 4 Sep 2017 09:03:40 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 03C1620A08; Mon, 4 Sep 2017 15:03:38 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id CA44120927;\n\tMon, 4 Sep 2017 15:03:37 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","From":"Maxime Ripard ","To":"Mauro Carvalho Chehab ,\n\tMark Rutland , Rob Herring ","Cc":"Laurent Pinchart ,\n\tlinux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka\n\t, Neil Webb , Richard Sproul\n\t, Alan Douglas , Steve Creaney\n\t, Thomas Petazzoni\n\t, Boris Brezillon\n\t, =?utf-8?q?Niklas_S=C3=B6derlund?=\n\t, Hans Verkuil ,\n\tSakari Ailus , \n\tBenoit Parrot , Maxime Ripard\n\t","Subject":"[PATCH v3 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device\n\tTree bindings","Date":"Mon, 4 Sep 2017 15:03:34 +0200","Message-Id":"<20170904130335.23280-2-maxime.ripard@free-electrons.com>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170904130335.23280-1-maxime.ripard@free-electrons.com>","References":"<20170904130335.23280-1-maxime.ripard@free-electrons.com>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to\n4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on\nthe hardware implementation.\n\nIt can operate with an external D-PHY, an internal one or no D-PHY at all\nin some configurations.\n\nAcked-by: Rob Herring \nAcked-by: Benoit Parrot \nSigned-off-by: Maxime Ripard \n---\n .../devicetree/bindings/media/cdns-csi2rx.txt | 98 ++++++++++++++++++++++\n 1 file changed, 98 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/cdns-csi2rx.txt","diff":"diff --git a/Documentation/devicetree/bindings/media/cdns-csi2rx.txt b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt\nnew file mode 100644\nindex 000000000000..2395030d8c72\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt\n@@ -0,0 +1,98 @@\n+Cadence MIPI-CSI2 RX controller\n+===============================\n+\n+The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI\n+lanes in input, and 4 different pixel streams in output.\n+\n+Required properties:\n+ - compatible: must be set to \"cdns,csi2rx\" and an SoC-specific compatible\n+ - reg: base address and size of the memory mapped region\n+ - clocks: phandles to the clocks driving the controller\n+ - clock-names: must contain:\n+ * sys_clk: main clock\n+ * p_clk: register bank clock\n+ * pixel_if[0-3]_clk: pixel stream output clock, one for each stream\n+ implemented in hardware, between 0 and 3\n+\n+Optional properties:\n+ - phys: phandle to the external D-PHY, phy-names must be provided\n+ - phy-names: must contain dphy, if the implementation uses an\n+ external D-PHY\n+\n+Required subnodes:\n+ - ports: A ports node with endpoint definitions as defined in\n+ Documentation/devicetree/bindings/media/video-interfaces.txt. The\n+ first port subnode should be the input endpoint, the next ones the\n+ output, one for each stream supported by the CSI2-RX controller.\n+ The ports ID must be the stream output number used in the\n+ implementation, plus 1.\n+\n+Example:\n+\n+csi2rx: csi-bridge@0d060000 {\n+\tcompatible = \"cdns,csi2rx\";\n+\treg = <0x0d060000 0x1000>;\n+\tclocks = <&byteclock>, <&byteclock>\n+\t\t <&coreclock>, <&coreclock>,\n+\t\t <&coreclock>, <&coreclock>;\n+\tclock-names = \"sys_clk\", \"p_clk\",\n+\t\t \"pixel_if0_clk\", \"pixel_if1_clk\",\n+\t\t \"pixel_if2_clk\", \"pixel_if3_clk\";\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\n+\t\t\tcsi2rx_in_sensor: endpoint {\n+\t\t\t\tremote-endpoint = <&sensor_out_csi2rx>;\n+\t\t\t\tclock-lanes = <0>;\n+\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\n+\t\t\tcsi2rx_out_grabber0: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber0_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\n+\t\t\tcsi2rx_out_grabber1: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber1_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\n+\t\t\tcsi2rx_out_grabber2: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber2_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <4>;\n+\n+\t\t\tcsi2rx_out_grabber3: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber3_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n","prefixes":["v3","1/2"]}