{"id":809429,"url":"http://patchwork.ozlabs.org/api/1.0/patches/809429/?format=json","project":{"id":19,"url":"http://patchwork.ozlabs.org/api/1.0/projects/19/?format=json","name":"Linux IMX development","link_name":"linux-imx","list_id":"linux-imx-kernel.lists.patchwork.ozlabs.org","list_email":"linux-imx-kernel@lists.patchwork.ozlabs.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170903224100.17893-3-stefan.bruens@rwth-aachen.de>","date":"2017-09-03T22:40:53","name":"[02/10] dmaengine: sun6i: Correct burst length field offsets for H3","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"de9dab911ca88652b420faace9a2b20efd11a299","submitter":{"id":67055,"url":"http://patchwork.ozlabs.org/api/1.0/people/67055/?format=json","name":"Stefan Brüns","email":"stefan.bruens@rwth-aachen.de"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-imx/patch/20170903224100.17893-3-stefan.bruens@rwth-aachen.de/mbox/","series":[{"id":1284,"url":"http://patchwork.ozlabs.org/api/1.0/series/1284/?format=json","date":"2017-09-03T22:40:55","name":"dmaengine: sun6i: Fixes for H3/A83T, enable A64","version":1,"mbox":"http://patchwork.ozlabs.org/series/1284/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809429/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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d=\"scan'208\";a=\"11607786\"","From":"=?utf-8?q?Stefan_Br=C3=BCns?= ","To":"","Subject":"[PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets\n\tfor H3","Date":"Mon, 4 Sep 2017 00:40:53 +0200","Message-ID":"<20170903224100.17893-3-stefan.bruens@rwth-aachen.de>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170903224100.17893-1-stefan.bruens@rwth-aachen.de>","References":"<20170903224100.17893-1-stefan.bruens@rwth-aachen.de>","MIME-Version":"1.0","X-Originating-IP":"[92.225.242.208]","X-ClientProxiedBy":"rwthex-w1-b.rwth-ad.de (2002:8682:1a9d::8682:1a9d) To\n\trwthex-w2-b.rwth-ad.de (2002:8682:1a9f::8682:1a9f)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170903_154140_062155_08A36579 ","X-CRM114-Status":"UNSURE ( 8.85 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.130.5.47 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Vinod Koul ,\n\tAndre Przywara , linux-kernel@vger.kernel.org,\n\tCode Kipper , Chen-Yu Tsai ,\n\tRob Herring , dmaengine@vger.kernel.org,\n\tMaxime Ripard ,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"},"content":"For the H3, the burst lengths field offsets in the channel configuration\nregister differs from earlier SoC generations.\n\nUsing the A31 register macros actually configured the H3 controller\ndo to bursts of length 1 always, which although working leads to higher\nbus utilisation.\n\nSigned-off-by: Stefan Brüns \n---\n drivers/dma/sun6i-dma.c | 28 +++++++++++++++++++++-------\n 1 file changed, 21 insertions(+), 7 deletions(-)","diff":"diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c\nindex 1d9b3be30d22..f1a139f0102f 100644\n--- a/drivers/dma/sun6i-dma.c\n+++ b/drivers/dma/sun6i-dma.c\n@@ -68,13 +68,15 @@\n #define DMA_CHAN_CFG_SRC_DRQ(x)\t\t((x) & 0x1f)\n #define DMA_CHAN_CFG_SRC_IO_MODE\tBIT(5)\n #define DMA_CHAN_CFG_SRC_LINEAR_MODE\t(0 << 5)\n-#define DMA_CHAN_CFG_SRC_BURST(x)\t(((x) & 0x3) << 7)\n+#define DMA_CHAN_CFG_SRC_BURST_A31(x)\t(((x) & 0x3) << 7)\n+#define DMA_CHAN_CFG_SRC_BURST_H3(x)\t(((x) & 0x3) << 6)\n #define DMA_CHAN_CFG_SRC_WIDTH(x)\t(((x) & 0x3) << 9)\n \n #define DMA_CHAN_CFG_DST_DRQ(x)\t\t(DMA_CHAN_CFG_SRC_DRQ(x) << 16)\n #define DMA_CHAN_CFG_DST_IO_MODE\t(DMA_CHAN_CFG_SRC_IO_MODE << 16)\n #define DMA_CHAN_CFG_DST_LINEAR_MODE\t(DMA_CHAN_CFG_SRC_LINEAR_MODE << 16)\n-#define DMA_CHAN_CFG_DST_BURST(x)\t(DMA_CHAN_CFG_SRC_BURST(x) << 16)\n+#define DMA_CHAN_CFG_DST_BURST_A31(x)\t(DMA_CHAN_CFG_SRC_BURST_A31(x) << 16)\n+#define DMA_CHAN_CFG_DST_BURST_H3(x)\t(DMA_CHAN_CFG_SRC_BURST_H3(x) << 16)\n #define DMA_CHAN_CFG_DST_WIDTH(x)\t(DMA_CHAN_CFG_SRC_WIDTH(x) << 16)\n \n #define DMA_CHAN_CUR_SRC\t0x10\n@@ -554,11 +556,17 @@ static int set_config(struct sun6i_dma_dev *sdev,\n \tif (dst_width < 0)\n \t\treturn dst_width;\n \n-\t*p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) |\n-\t\tDMA_CHAN_CFG_SRC_WIDTH(src_width) |\n-\t\tDMA_CHAN_CFG_DST_BURST(dst_burst) |\n+\t*p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) |\n \t\tDMA_CHAN_CFG_DST_WIDTH(dst_width);\n \n+\tif (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) {\n+\t\t*p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_H3(dst_burst);\n+\t} else {\n+\t\t*p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_A31(dst_burst);\n+\t}\n+\n \treturn 0;\n }\n \n@@ -601,11 +609,17 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(\n \t\tDMA_CHAN_CFG_DST_DRQ(DRQ_SDRAM) |\n \t\tDMA_CHAN_CFG_DST_LINEAR_MODE |\n \t\tDMA_CHAN_CFG_SRC_LINEAR_MODE |\n-\t\tDMA_CHAN_CFG_SRC_BURST(burst) |\n \t\tDMA_CHAN_CFG_SRC_WIDTH(width) |\n-\t\tDMA_CHAN_CFG_DST_BURST(burst) |\n \t\tDMA_CHAN_CFG_DST_WIDTH(width);\n \n+\tif (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) {\n+\t\tv_lli->cfg |= DMA_CHAN_CFG_SRC_BURST_H3(burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_H3(burst);\n+\t} else {\n+\t\tv_lli->cfg |= DMA_CHAN_CFG_SRC_BURST_A31(burst) |\n+\t\t\t DMA_CHAN_CFG_DST_BURST_A31(burst);\n+\t}\n+\n \tsun6i_dma_lli_add(NULL, v_lli, p_lli, txd);\n \n \tsun6i_dma_dump_lli(vchan, v_lli);\n","prefixes":["02/10"]}