{"id":809058,"url":"http://patchwork.ozlabs.org/api/1.0/patches/809058/?format=json","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.0/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<1504351729-135932-1-git-send-email-hjc@rock-chips.com>","date":"2017-09-02T11:28:47","name":"[v8,1/3] dt-bindings: display: Add Document for Rockchip Soc LVDS","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"99b0fdca760ab9113ac24f50255a83e05304d688","submitter":{"id":72133,"url":"http://patchwork.ozlabs.org/api/1.0/people/72133/?format=json","name":"Huang Jiachai","email":"hjc@rock-chips.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504351729-135932-1-git-send-email-hjc@rock-chips.com/mbox/","series":[{"id":1147,"url":"http://patchwork.ozlabs.org/api/1.0/series/1147/?format=json","date":"2017-09-02T11:28:47","name":"Add support Rockchip Soc LVDS","version":8,"mbox":"http://patchwork.ozlabs.org/series/1147/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809058/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkv5D1jQsz9rxl\n\tfor ;\n\tSat, 2 Sep 2017 21:29:04 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752297AbdIBL3A (ORCPT\n\t);\n\tSat, 2 Sep 2017 07:29:00 -0400","from regular1.263xmail.com ([211.150.99.139]:40287 \"EHLO\n\tregular1.263xmail.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751570AbdIBL3A (ORCPT\n\t); Sat, 2 Sep 2017 07:29:00 -0400","from hjc?rock-chips.com (unknown [192.168.167.233])\n\tby regular1.263xmail.com (Postfix) with ESMTP id DA6CE52AE;\n\tSat, 2 Sep 2017 19:28:49 +0800 (CST)","from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 41209381;\n\tSat, 2 Sep 2017 19:28:49 +0800 (CST)","from localhost.localdomain (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith ESMTP id 29552QUOP5V;\n\tSat, 02 Sep 2017 19:28:50 +0800 (CST)"],"X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"hjc@rock-chips.com","X-FST-TO":"mark.yao@rock-chips.com","X-SENDER-IP":"58.22.7.114","X-LOGIN-NAME":"hjc@rock-chips.com","X-UNIQUE-TAG":"<4b8e88e2a9d821b00111509b2248e220>","X-ATTACHMENT-NUM":"0","X-SENDER":"hjc@rock-chips.com","X-DNS-TYPE":"0","From":"Sandy Huang ","To":"Mark Yao , David Airlie ,\n\tRob Herring , Mark Rutland ,\n\tHeiko Stuebner ","Cc":"Sandy Huang , dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"[PATCH v8 1/3] dt-bindings: display: Add Document for Rockchip Soc\n\tLVDS","Date":"Sat, 2 Sep 2017 19:28:47 +0800","Message-Id":"<1504351729-135932-1-git-send-email-hjc@rock-chips.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504351723-135876-1-git-send-email-hjc@rock-chips.com>","References":"<1504351723-135876-1-git-send-email-hjc@rock-chips.com>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"This patch add Document for Rockchip Soc RK3288 LVDS,\nThis based on the patches from Mark yao and Heiko Stuebner.\n\nSigned-off-by: Mark yao \nSigned-off-by: Heiko Stuebner \nSigned-off-by: Sandy Huang \n---\nChange the Signed-off order\n\n .../bindings/display/rockchip/rockchip-lvds.txt | 99 ++++++++++++++++++++++\n 1 file changed, 99 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt","diff":"diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt\nnew file mode 100644\nindex 0000000..da6939e\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt\n@@ -0,0 +1,99 @@\n+Rockchip RK3288 LVDS interface\n+================================\n+\n+Required properties:\n+- compatible: matching the soc type, one of\n+\t- \"rockchip,rk3288-lvds\";\n+\n+- reg: physical base address of the controller and length\n+\tof memory mapped region.\n+- clocks: must include clock specifiers corresponding to entries in the\n+\tclock-names property.\n+- clock-names: must contain \"pclk_lvds\"\n+\n+- avdd1v0-supply: regulator phandle for 1.0V analog power\n+- avdd1v8-supply: regulator phandle for 1.8V analog power\n+- avdd3v3-supply: regulator phandle for 3.3V analog power\n+\n+- rockchip,grf: phandle to the general register files syscon\n+- rockchip,output: \"rgb\", \"lvds\" or \"duallvds\", This describes the output interface\n+\n+Optional properties:\n+- pinctrl-names: must contain a \"lcdc\" entry.\n+- pinctrl-0: pin control group to be used for this controller.\n+\n+Required nodes:\n+\n+The lvds has two video ports as described by\n+\tDocumentation/devicetree/bindings/media/video-interfaces.txt\n+Their connections are modeled using the OF graph bindings specified in\n+\tDocumentation/devicetree/bindings/graph.txt.\n+\n+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl\n+- video port 1 for either a panel or subsequent encoder\n+\n+the lvds panel described by\n+\tDocumentation/devicetree/bindings/display/panel/simple-panel.txt\n+\n+Panel required properties:\n+- ports for remote LVDS output\n+\n+Panel optional properties:\n+- data-mapping: should be \"vesa-24\",\"jeida-24\" or \"jeida-18\".\n+This describes decribed by:\n+\tDocumentation/devicetree/bindings/display/panel/panel-lvds.txt\n+\n+Example:\n+\n+lvds_panel: lvds-panel {\n+\tcompatible = \"auo,b101ean01\";\n+\tenable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;\n+\tdata-mapping = \"jeida-24\";\n+\n+\tports {\n+\t\tpanel_in_lvds: endpoint {\n+\t\t\tremote-endpoint = <&lvds_out_panel>;\n+\t\t};\n+\t};\n+};\n+\n+For Rockchip RK3288:\n+\n+\tlvds: lvds@ff96c000 {\n+\t\tcompatible = \"rockchip,rk3288-lvds\";\n+\t\trockchip,grf = <&grf>;\n+\t\treg = <0xff96c000 0x4000>;\n+\t\tclocks = <&cru PCLK_LVDS_PHY>;\n+\t\tclock-names = \"pclk_lvds\";\n+\t\tpinctrl-names = \"lcdc\";\n+\t\tpinctrl-0 = <&lcdc_ctl>;\n+\t\tavdd1v0-supply = <&vdd10_lcd>;\n+\t\tavdd1v8-supply = <&vcc18_lcd>;\n+\t\tavdd3v3-supply = <&vcca_33>;\n+\t\trockchip,output = \"rgb\";\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tlvds_in: port@0 {\n+\t\t\t\treg = <0>;\n+\n+\t\t\t\tlvds_in_vopb: endpoint@0 {\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tremote-endpoint = <&vopb_out_lvds>;\n+\t\t\t\t};\n+\t\t\t\tlvds_in_vopl: endpoint@1 {\n+\t\t\t\t\treg = <1>;\n+\t\t\t\t\tremote-endpoint = <&vopl_out_lvds>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tlvds_out: port@1 {\n+\t\t\t\treg = <1>;\n+\n+\t\t\t\tlvds_out_panel: endpoint {\n+\t\t\t\t\tremote-endpoint = <&panel_in_lvds>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n","prefixes":["v8","1/3"]}