{"id":808966,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808966/?format=json","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.0/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170901185736.28051-8-thierry.reding@gmail.com>","date":"2017-09-01T18:57:27","name":"[07/16] gpio: Move irq_chained_parent to struct gpio_irq_chip","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"b03fe3e135c361f967328c0e41de4fab112e68cc","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/1.0/people/26234/?format=json","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901185736.28051-8-thierry.reding@gmail.com/mbox/","series":[{"id":1099,"url":"http://patchwork.ozlabs.org/api/1.0/series/1099/?format=json","date":"2017-09-01T18:57:20","name":"gpio: Tight IRQ chip integration and banked infrastructure","version":1,"mbox":"http://patchwork.ozlabs.org/series/1099/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808966/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"nDZzXUm3\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xkT8v0b0rz9sQl\n\tfor ;\n\tSat, 2 Sep 2017 05:00:47 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752619AbdIATAe (ORCPT );\n\tFri, 1 Sep 2017 15:00:34 -0400","from mail-wr0-f196.google.com ([209.85.128.196]:38801 \"EHLO\n\tmail-wr0-f196.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752485AbdIAS5w (ORCPT\n\t); Fri, 1 Sep 2017 14:57:52 -0400","by mail-wr0-f196.google.com with SMTP id j3so475830wrb.5;\n\tFri, 01 Sep 2017 11:57:51 -0700 (PDT)","from localhost\n\t(p200300E41BD6D60076D02BFFFE273F51.dip0.t-ipconnect.de.\n\t[2003:e4:1bd6:d600:76d0:2bff:fe27:3f51])\n\tby smtp.gmail.com with ESMTPSA id\n\tk195sm885803wmg.43.2017.09.01.11.57.49\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tFri, 01 Sep 2017 11:57:49 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=lG2Dm9F5yVIXwgLQuCKN2MDVMOVbu4nMgk53BtrqMBE=;\n\tb=nDZzXUm3EIRWHEAj+4vPrsdUHJrzisbKVf5yTRHfMcR0co6uzTt5WgL4sqv6Lp+oeM\n\t7WhcYftD/N6h4yGK3gysjuo6uqT7Ws+ZB4gtyZYw491BSMm4F8PPrZvHaI97bTcj5zrf\n\tIzVoEoawHWkuXuoGmqauYtrYu57KO0hnwc0b4Yl5kqB/qIFSmh72OxUiZLioEjSmMIDs\n\tjIk8jUOdCuy8KeQ6XIHQbRjhPC9wD4LA4cejZtB5DSrjC67sCYjK6EtnZc12Yx9YaoUb\n\tLpuAIMJFPTAcwNoiLxbt/4NSm6oXqSdd08Ae4L/MCXHddmOVDcKUQcp9+8+4Izv/JU0V\n\tOGjQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=lG2Dm9F5yVIXwgLQuCKN2MDVMOVbu4nMgk53BtrqMBE=;\n\tb=uArkVWtGoll710gF/NZQ7IaweR8tnkiWrTjcV0iuA2N3VJu18uhLseSBZeUv2EhQP1\n\tImZwzB+1bUQqQL+WhoAOt+lOFPqlJXRUrg/cC+ERbj+qNshfjnUEgZIdcf5HHNtWSXxl\n\tD/8l0MCNzowje5bHxyY1HsPsgy9O0db3EEDTsKSQ+P3YcUhE1gvF0ODJWcnwg/H0OVUh\n\t01H7Vl4+FnhAfxA6thJTx+5VwWP1UZX9pyEkDuvzk3kPogdVN4hWVV6CBgI85h5rnCoN\n\tmNs0CFNPb1I8wKSQ4eQxa2ZCnyxYFtM9yMTJTZlJ4DZxBtnPQZKq01P67mGl1rK2FnOp\n\t23eQ==","X-Gm-Message-State":"AHPjjUjwolmnnsKQodbLm2h/BtK2K5oQ31rFzlakyiCxcavDNXFKg+pO\n\t2LU8Ql6J5UGQlg==","X-Google-Smtp-Source":"ADKCNb6VCy84xCW6WPDEssD0P8qsoIqzJ68+zJQsjp2t+fgfc+l4viWlAv0rxJ4nX3huBNa4StjmDQ==","X-Received":"by 10.223.186.4 with SMTP id o4mr1917722wrg.236.1504292270451;\n\tFri, 01 Sep 2017 11:57:50 -0700 (PDT)","From":"Thierry Reding ","To":"Linus Walleij ","Cc":"Jonathan Hunter , linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"[PATCH 07/16] gpio: Move irq_chained_parent to struct gpio_irq_chip","Date":"Fri, 1 Sep 2017 20:57:27 +0200","Message-Id":"<20170901185736.28051-8-thierry.reding@gmail.com>","X-Mailer":"git-send-email 2.13.3","In-Reply-To":"<20170901185736.28051-1-thierry.reding@gmail.com>","References":"<20170901185736.28051-1-thierry.reding@gmail.com>","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"},"content":"From: Thierry Reding \n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding \n---\n drivers/gpio/gpiolib.c | 8 ++------\n include/linux/gpio/driver.h | 4 ----\n 2 files changed, 2 insertions(+), 10 deletions(-)","diff":"diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex 774d6047116a..f09cc89929f0 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1580,7 +1580,8 @@ static void gpiochip_set_cascaded_irqchip(struct gpio_chip *gpiochip,\n \t\tirq_set_chained_handler_and_data(parent_irq, parent_handler,\n \t\t\t\t\t\t gpiochip);\n \n-\t\tgpiochip->irq_chained_parent = parent_irq;\n+\t\tgpiochip->irq.parents = &parent_irq;\n+\t\tgpiochip->irq.num_parents = 1;\n \t}\n \n \t/* Set the parent IRQ for all affected IRQs */\n@@ -1853,11 +1854,6 @@ static void gpiochip_irqchip_remove(struct gpio_chip *gpiochip)\n \n \tacpi_gpiochip_free_interrupts(gpiochip);\n \n-\tif (gpiochip->irq_chained_parent) {\n-\t\tirq_set_chained_handler(gpiochip->irq_chained_parent, NULL);\n-\t\tirq_set_handler_data(gpiochip->irq_chained_parent, NULL);\n-\t}\n-\n \tif (gpiochip->irq.chip) {\n \t\tstruct gpio_irq_chip *irq = &gpiochip->irq;\n \t\tunsigned int i;\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex bcf93afddfa6..c3eafd874884 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -176,9 +176,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n *\tsafely.\n * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n *\tdirection safely.\n- * @irq_chained_parent: GPIO IRQ chip parent/bank linux irq number,\n- *\tprovided by GPIO driver for chained interrupt (not for nested\n- *\tinterrupts).\n * @irq_nested: True if set the interrupt handling is nested.\n * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all\n *\tbits set to one\n@@ -251,7 +248,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tunsigned int\t\tirq_chained_parent;\n \tbool\t\t\tirq_nested;\n \tbool\t\t\tirq_need_valid_mask;\n \tunsigned long\t\t*irq_valid_mask;\n","prefixes":["07/16"]}