{"id":808948,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808948/?format=json","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.0/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170901185736.28051-9-thierry.reding@gmail.com>","date":"2017-09-01T18:57:28","name":"[08/16] gpio: Move irq_nested into struct gpio_irq_chip","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"4e3904ebea4ca5768e5ed8f00c2c406413c62133","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/1.0/people/26234/?format=json","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20170901185736.28051-9-thierry.reding@gmail.com/mbox/","series":[{"id":1099,"url":"http://patchwork.ozlabs.org/api/1.0/series/1099/?format=json","date":"2017-09-01T18:57:20","name":"gpio: Tight IRQ chip integration and banked infrastructure","version":1,"mbox":"http://patchwork.ozlabs.org/series/1099/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808948/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=0jQSsIRyQ2mDinfnKtVeYyb7EEdXnkvYSys82YoLMHU=;\n\tb=ekMaM4KVrsrPDfdslEMjy+kofzGUTrykm8Xe3pGur1tzJ7D08PD8isceup7p1KZ/ph\n\tPKnYLRs37ac4GU5dH9UwraDSQznOl1UNLMphZUfseGeeX2HU87X7ihgSuf479g+A/mI8\n\tIQp0Kpiw8b/F9wRdmBCpjWGWoD94kb7DOYQVZYGQiDM2719VrCQv4NkmyTSh9cAJUkss\n\tb6u4/jRFwn1VC0zAIV8MfHWcnWtf6gN23ogoxvUl2viDoqxQu85Bnt2BSMIhNP16Dh84\n\t9hunLrNv3g84nuF7xS/DQRuzc9YuOO0yUNxSFFcyw/fAEjBrU2Bah/+lZzS4xTTFmNlc\n\tC0uw==","X-Gm-Message-State":"AHPjjUgdnfb+PD4tO0CS2GlJJ12j9tNum4kQDI5bjXHNW1v/Gw9g8wUr\n\tAMOyJqaYgpddWA==","X-Google-Smtp-Source":"ADKCNb4NQTqv3P2Mpm0pFqxsYtSjeX7MabV3D9W5dII9Y91h/1OiTtlmyh1sppdqxgAZueS7oYotFw==","X-Received":"by 10.28.94.84 with SMTP id s81mr1020631wmb.3.1504292271937;\n\tFri, 01 Sep 2017 11:57:51 -0700 (PDT)","From":"Thierry Reding ","To":"Linus Walleij ","Cc":"Jonathan Hunter , linux-gpio@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"[PATCH 08/16] gpio: Move irq_nested into struct gpio_irq_chip","Date":"Fri, 1 Sep 2017 20:57:28 +0200","Message-Id":"<20170901185736.28051-9-thierry.reding@gmail.com>","X-Mailer":"git-send-email 2.13.3","In-Reply-To":"<20170901185736.28051-1-thierry.reding@gmail.com>","References":"<20170901185736.28051-1-thierry.reding@gmail.com>","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"},"content":"From: Thierry Reding \n\nIn order to consolidate the multiple ways to associate an IRQ chip with\na GPIO chip, move more fields into the new struct gpio_irq_chip.\n\nSigned-off-by: Thierry Reding \n---\n drivers/gpio/gpiolib.c | 12 ++++++------\n include/linux/gpio/driver.h | 9 +++++++--\n 2 files changed, 13 insertions(+), 8 deletions(-)","diff":"diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c\nindex f09cc89929f0..f506473f5c70 100644\n--- a/drivers/gpio/gpiolib.c\n+++ b/drivers/gpio/gpiolib.c\n@@ -1624,7 +1624,7 @@ void gpiochip_set_nested_irqchip(struct gpio_chip *gpiochip,\n \t\t\t\t struct irq_chip *irqchip,\n \t\t\t\t unsigned int parent_irq)\n {\n-\tif (!gpiochip->irq_nested) {\n+\tif (!gpiochip->irq.nested) {\n \t\tchip_err(gpiochip, \"tried to nest a chained gpiochip\\n\");\n \t\treturn;\n \t}\n@@ -1659,7 +1659,7 @@ int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,\n \tirq_set_lockdep_class(irq, chip->lock_key);\n \tirq_set_chip_and_handler(irq, chip->irq.chip, chip->irq.handler);\n \t/* Chips that use nested thread handlers have them marked */\n-\tif (chip->irq_nested)\n+\tif (chip->irq.nested)\n \t\tirq_set_nested_thread(irq, 1);\n \tirq_set_noprobe(irq);\n \n@@ -1678,7 +1678,7 @@ void gpiochip_irq_unmap(struct irq_domain *d, unsigned int irq)\n {\n \tstruct gpio_chip *chip = d->host_data;\n \n-\tif (chip->irq_nested)\n+\tif (chip->irq.nested)\n \t\tirq_set_nested_thread(irq, 0);\n \tirq_set_chip_and_handler(irq, NULL, NULL);\n \tirq_set_chip_data(irq, NULL);\n@@ -1811,9 +1811,9 @@ static int gpiochip_add_irqchip(struct gpio_chip *gpiochip)\n \t\t\t\t\t\t\t data);\n \t\t}\n \n-\t\tgpiochip->irq_nested = false;\n+\t\tgpiochip->irq.nested = false;\n \t} else {\n-\t\tgpiochip->irq_nested = true;\n+\t\tgpiochip->irq.nested = true;\n \t}\n \n \t/*\n@@ -1930,7 +1930,7 @@ int gpiochip_irqchip_add_key(struct gpio_chip *gpiochip,\n \t\tpr_err(\"missing gpiochip .dev parent pointer\\n\");\n \t\treturn -EINVAL;\n \t}\n-\tgpiochip->irq_nested = nested;\n+\tgpiochip->irq.nested = nested;\n \tof_node = gpiochip->parent->of_node;\n #ifdef CONFIG_OF_GPIO\n \t/*\ndiff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h\nindex c3eafd874884..7d632a8932be 100644\n--- a/include/linux/gpio/driver.h\n+++ b/include/linux/gpio/driver.h\n@@ -107,6 +107,13 @@ struct gpio_irq_chip {\n \t * A list of interrupt parents for each line of a GPIO chip.\n \t */\n \tunsigned int *map;\n+\n+\t/**\n+\t * @nested:\n+\t *\n+\t * True if set the interrupt handling is nested.\n+\t */\n+\tbool nested;\n };\n \n static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n@@ -176,7 +183,6 @@ static inline struct gpio_irq_chip *to_gpio_irq_chip(struct irq_chip *chip)\n *\tsafely.\n * @bgpio_dir: shadowed direction register for generic GPIO to clear/set\n *\tdirection safely.\n- * @irq_nested: True if set the interrupt handling is nested.\n * @irq_need_valid_mask: If set core allocates @irq_valid_mask with all\n *\tbits set to one\n * @irq_valid_mask: If not %NULL holds bitmask of GPIOs which are valid to\n@@ -248,7 +254,6 @@ struct gpio_chip {\n \t * With CONFIG_GPIOLIB_IRQCHIP we get an irqchip inside the gpiolib\n \t * to handle IRQs for most practical cases.\n \t */\n-\tbool\t\t\tirq_nested;\n \tbool\t\t\tirq_need_valid_mask;\n \tunsigned long\t\t*irq_valid_mask;\n \tstruct lock_class_key\t*lock_key;\n","prefixes":["08/16"]}