{"id":808569,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808569/?format=json","project":{"id":3,"url":"http://patchwork.ozlabs.org/api/1.0/projects/3/?format=json","name":"Linux MTD development","link_name":"linux-mtd","list_id":"linux-mtd.lists.infradead.org","list_email":"linux-mtd@lists.infradead.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<1504252841-2445-5-git-send-email-bmeng.cn@gmail.com>","date":"2017-09-01T08:00:35","name":"[04/10] spi-nor: intel-spi: Check transfer length in the HW/SW cycle","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"3c8cf2f4b09f3a45395c243ab9408b8f12b87a53","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/1.0/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":63396,"url":"http://patchwork.ozlabs.org/api/1.0/users/63396/?format=json","username":"cpitchen","first_name":"Cyrille","last_name":"Pitchen","email":"cyrille.pitchen@atmel.com"},"mbox":"http://patchwork.ozlabs.org/project/linux-mtd/patch/1504252841-2445-5-git-send-email-bmeng.cn@gmail.com/mbox/","series":[{"id":969,"url":"http://patchwork.ozlabs.org/api/1.0/series/969/?format=json","date":"2017-09-01T08:00:33","name":"spi-nor: intel-spi: Various fixes and enhancements","version":1,"mbox":"http://patchwork.ozlabs.org/series/969/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808569/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-mtd\" ","Errors-To":"linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"},"content":"Intel SPI controller only has a 64 bytes FIFO. This adds a sanity\ncheck before triggering any HW/SW sequencer work.\n\nAdditionally for the SW sequencer, if given data length is zero,\nwe should not mark the 'Data Cycle' bit.\n\nSigned-off-by: Bin Meng \n---\n\n drivers/mtd/spi-nor/intel-spi.c | 12 ++++++++++--\n 1 file changed, 10 insertions(+), 2 deletions(-)","diff":"diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c\nindex 263c6ab..c4a9de6 100644\n--- a/drivers/mtd/spi-nor/intel-spi.c\n+++ b/drivers/mtd/spi-nor/intel-spi.c\n@@ -399,6 +399,9 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n \t\treturn -EINVAL;\n \t}\n \n+\tif (len > INTEL_SPI_FIFO_SZ)\n+\t\treturn -EINVAL;\n+\n \tval |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;\n \tval |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;\n \tval |= HSFSTS_CTL_FGO;\n@@ -419,14 +422,19 @@ static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n \n static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len)\n {\n-\tu32 val, status;\n+\tu32 val = 0, status;\n \tint ret;\n \n \tret = intel_spi_opcode_index(ispi, opcode);\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tval = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;\n+\tif (len > INTEL_SPI_FIFO_SZ)\n+\t\treturn -EINVAL;\n+\n+\t/* Only mark 'Data Cycle' bit when there is data to be transferred */\n+\tif (len > 0)\n+\t\tval = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;\n \tval |= ret << SSFSTS_CTL_COP_SHIFT;\n \tval |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;\n \tval |= SSFSTS_CTL_SCGO;\n","prefixes":["04/10"]}