{"id":808552,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808552/?format=json","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.0/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<1504251255-20469-2-git-send-email-pierre-yves.mordret@st.com>","date":"2017-09-01T07:34:11","name":"[RESEND,v3,1/5] dt-bindings: i2c-stm32: Document the STM32F7 I2C bindings","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"87cb46eec4a59af078189b32735be034b947861b","submitter":{"id":71499,"url":"http://patchwork.ozlabs.org/api/1.0/people/71499/?format=json","name":"Pierre Yves MORDRET","email":"pierre-yves.mordret@st.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504251255-20469-2-git-send-email-pierre-yves.mordret@st.com/mbox/","series":[{"id":964,"url":"http://patchwork.ozlabs.org/api/1.0/series/964/?format=json","date":"2017-09-01T07:34:11","name":"Add support for the STM32F7 I2C","version":3,"mbox":"http://patchwork.ozlabs.org/series/964/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808552/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xk9y44HRzz9sMN\n\tfor ;\n\tFri, 1 Sep 2017 17:35:24 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751398AbdIAHfW (ORCPT\n\t);\n\tFri, 1 Sep 2017 03:35:22 -0400","from mx08-00178001.pphosted.com ([91.207.212.93]:55616 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751354AbdIAHfV (ORCPT\n\t); Fri, 1 Sep 2017 03:35:21 -0400","from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv817Xq9i026789; Fri, 1 Sep 2017 09:34:32 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2cq1810tcc-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tFri, 01 Sep 2017 09:34:32 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C721734;\n\tFri, 1 Sep 2017 07:34:30 +0000 (GMT)","from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A0F8011EC;\n\tFri, 1 Sep 2017 07:34:30 +0000 (GMT)","from localhost (10.75.127.51) by SFHDAG5NODE2.st.com (10.75.127.14)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tFri, 1 Sep 2017 09:34:30 +0200"],"From":"Pierre-Yves MORDRET ","To":"Wolfram Sang , Rob Herring ,\n\tMark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\t, ,\n\t, ","CC":"Pierre-Yves MORDRET ","Subject":"[RESEND PATCH v3 1/5] dt-bindings: i2c-stm32: Document the STM32F7\n\tI2C bindings","Date":"Fri, 1 Sep 2017 09:34:11 +0200","Message-ID":"<1504251255-20469-2-git-send-email-pierre-yves.mordret@st.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504251255-20469-1-git-send-email-pierre-yves.mordret@st.com>","References":"<1504251255-20469-1-git-send-email-pierre-yves.mordret@st.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.75.127.51]","X-ClientProxiedBy":"SFHDAG2NODE3.st.com (10.75.127.6) To SFHDAG5NODE2.st.com\n\t(10.75.127.14)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-01_02:, , signatures=0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"This patch adds the documentation of device tree bindings for STM32F7 I2C\n\nSigned-off-by: M'boumba Cedric Madianga \nSigned-off-by: Pierre-Yves MORDRET \nAcked-by: Rob Herring \n---\n Version history:\n v3:\n * None\n v2:\n * Remove i2c-timing binding in order to use generic bindings SCL\n Rising and Falling time instead\n---\n---\n .../devicetree/bindings/i2c/i2c-stm32.txt | 29 +++++++++++++++++++---\n 1 file changed, 26 insertions(+), 3 deletions(-)","diff":"diff --git a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt\nindex 78eaf7b..3b54899 100644\n--- a/Documentation/devicetree/bindings/i2c/i2c-stm32.txt\n+++ b/Documentation/devicetree/bindings/i2c/i2c-stm32.txt\n@@ -1,7 +1,9 @@\n * I2C controller embedded in STMicroelectronics STM32 I2C platform\n \n Required properties :\n-- compatible : Must be \"st,stm32f4-i2c\"\n+- compatible : Must be one of the following\n+ - \"st,stm32f4-i2c\"\n+ - \"st,stm32f7-i2c\"\n - reg : Offset and length of the register set for the device\n - interrupts : Must contain the interrupt id for I2C event and then the\n interrupt id for I2C error.\n@@ -14,8 +16,16 @@ Required properties :\n \n Optional properties :\n - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,\n- the default 100 kHz frequency will be used. As only Normal and Fast modes\n- are supported, possible values are 100000 and 400000.\n+ the default 100 kHz frequency will be used.\n+ For STM32F4 SoC Standard-mode and Fast-mode are supported, possible values are\n+ 100000 and 400000.\n+ For STM32F7 SoC, Standard-mode, Fast-mode and Fast-mode Plus are supported,\n+ possible values are 100000, 400000 and 1000000.\n+- i2c-scl-rising-time-ns : Only for STM32F7, I2C SCL Rising time for the board\n+ (default: 25)\n+- i2c-scl-falling-time-ns : Only for STM32F7, I2C SCL Falling time for the board\n+ (default: 10)\n+ I2C Timings are derived from these 2 values\n \n Example :\n \n@@ -31,3 +41,16 @@ Example :\n \t\tpinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;\n \t\tpinctrl-names = \"default\";\n \t};\n+\n+\ti2c@40005400 {\n+\t\tcompatible = \"st,stm32f7-i2c\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x40005400 0x400>;\n+\t\tinterrupts = <31>,\n+\t\t\t <32>;\n+\t\tresets = <&rcc STM32F7_APB1_RESET(I2C1)>;\n+\t\tclocks = <&rcc 1 CLK_I2C1>;\n+\t\tpinctrl-0 = <&i2c1_sda_pin>, <&i2c1_scl_pin>;\n+\t\tpinctrl-names = \"default\";\n+\t};\n","prefixes":["RESEND","v3","1/5"]}