{"id":808488,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808488/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20170901001502.29915-8-jsnow@redhat.com>","date":"2017-09-01T00:15:00","name":"[v3,7/9] AHCI: Rework IRQ constants","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"719759defe33ca9d54fd0b9e644343bfcc271d6a","submitter":{"id":64343,"url":"http://patchwork.ozlabs.org/api/1.0/people/64343/?format=json","name":"John Snow","email":"jsnow@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170901001502.29915-8-jsnow@redhat.com/mbox/","series":[{"id":931,"url":"http://patchwork.ozlabs.org/api/1.0/series/931/?format=json","date":"2017-09-01T00:14:53","name":"IDE: replace printfs with tracing","version":3,"mbox":"http://patchwork.ozlabs.org/series/931/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808488/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx10.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=jsnow@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xk0H64wZZz9s8J\n\tfor ;\n\tFri, 1 Sep 2017 10:19:30 +1000 (AEST)","from localhost ([::1]:34605 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dnZgG-000317-NI\n\tfor incoming@patchwork.ozlabs.org; Thu, 31 Aug 2017 20:19:28 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:51782)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dnZcl-0000Nw-SH\n\tfor qemu-devel@nongnu.org; Thu, 31 Aug 2017 20:15:53 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dnZci-0004rx-MI\n\tfor qemu-devel@nongnu.org; Thu, 31 Aug 2017 20:15:51 -0400","from mx1.redhat.com ([209.132.183.28]:58034)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dnZce-0004iX-Fp; Thu, 31 Aug 2017 20:15:44 -0400","from smtp.corp.redhat.com\n\t(int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 92BEB61485;\n\tFri, 1 Sep 2017 00:15:43 +0000 (UTC)","from probe.bos.redhat.com (dhcp-17-130.bos.redhat.com\n\t[10.18.17.130])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 65653A3975;\n\tFri, 1 Sep 2017 00:15:41 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 92BEB61485","From":"John Snow ","To":"qemu-block@nongnu.org","Date":"Thu, 31 Aug 2017 20:15:00 -0400","Message-Id":"<20170901001502.29915-8-jsnow@redhat.com>","In-Reply-To":"<20170901001502.29915-1-jsnow@redhat.com>","References":"<20170901001502.29915-1-jsnow@redhat.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.13","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.39]);\n\tFri, 01 Sep 2017 00:15:43 +0000 (UTC)","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PATCH v3 7/9] AHCI: Rework IRQ constants","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"John Snow , qemu-devel@nongnu.org, stefanha@redhat.com,\n\tf4bug@amsat.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Create a new enum so that we can name the IRQ bits, which will make debugging\nthem a little nicer if we can print them out. Not handled in this patch, but\nthis will make it possible to get a nice debug printf detailing exactly which\nstatus bits are set, as it can be multiple at any given time.\n\nAs a consequence of this patch, it is no longer possible to set multiple IRQ\ncodes at once, but nothing was utilizing this ability anyway.\n\nReviewed-by: Philippe Mathieu-Daudé \nSigned-off-by: John Snow \n---\n hw/ide/ahci.c | 49 ++++++++++++++++++++++++++++++++++++++-----------\n hw/ide/ahci_internal.h | 44 +++++++++++++++++++++++++++++++++++---------\n hw/ide/trace-events | 2 +-\n 3 files changed, 74 insertions(+), 21 deletions(-)","diff":"diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c\nindex c60a000..82cc196 100644\n--- a/hw/ide/ahci.c\n+++ b/hw/ide/ahci.c\n@@ -56,6 +56,27 @@ static bool ahci_map_fis_address(AHCIDevice *ad);\n static void ahci_unmap_clb_address(AHCIDevice *ad);\n static void ahci_unmap_fis_address(AHCIDevice *ad);\n \n+static const char *AHCIPortIRQ_lookup[AHCI_PORT_IRQ__COUNT] = {\n+ [AHCI_PORT_IRQ_BIT_DHRS] = \"DHRS\",\n+ [AHCI_PORT_IRQ_BIT_PSS] = \"PSS\",\n+ [AHCI_PORT_IRQ_BIT_DSS] = \"DSS\",\n+ [AHCI_PORT_IRQ_BIT_SDBS] = \"SDBS\",\n+ [AHCI_PORT_IRQ_BIT_UFS] = \"UFS\",\n+ [AHCI_PORT_IRQ_BIT_DPS] = \"DPS\",\n+ [AHCI_PORT_IRQ_BIT_PCS] = \"PCS\",\n+ [AHCI_PORT_IRQ_BIT_DMPS] = \"DMPS\",\n+ [8 ... 21] = \"RESERVED\",\n+ [AHCI_PORT_IRQ_BIT_PRCS] = \"PRCS\",\n+ [AHCI_PORT_IRQ_BIT_IPMS] = \"IPMS\",\n+ [AHCI_PORT_IRQ_BIT_OFS] = \"OFS\",\n+ [25] = \"RESERVED\",\n+ [AHCI_PORT_IRQ_BIT_INFS] = \"INFS\",\n+ [AHCI_PORT_IRQ_BIT_IFS] = \"IFS\",\n+ [AHCI_PORT_IRQ_BIT_HBDS] = \"HBDS\",\n+ [AHCI_PORT_IRQ_BIT_HBFS] = \"HBFS\",\n+ [AHCI_PORT_IRQ_BIT_TFES] = \"TFES\",\n+ [AHCI_PORT_IRQ_BIT_CPDS] = \"CPDS\"\n+};\n \n static uint32_t ahci_port_read(AHCIState *s, int port, int offset)\n {\n@@ -170,12 +191,18 @@ static void ahci_check_irq(AHCIState *s)\n }\n \n static void ahci_trigger_irq(AHCIState *s, AHCIDevice *d,\n- int irq_type)\n+ enum AHCIPortIRQ irqbit)\n {\n- DPRINTF(d->port_no, \"trigger irq %#x -> %x\\n\",\n- irq_type, d->port_regs.irq_mask & irq_type);\n+ g_assert(irqbit >= 0 && irqbit < 32);\n+ uint32_t irq = 1U << irqbit;\n+ uint32_t irqstat = d->port_regs.irq_stat | irq;\n \n- d->port_regs.irq_stat |= irq_type;\n+ trace_ahci_trigger_irq(s, d->port_no,\n+ AHCIPortIRQ_lookup[irqbit], irq,\n+ d->port_regs.irq_stat, irqstat,\n+ irqstat & d->port_regs.irq_mask);\n+\n+ d->port_regs.irq_stat = irqstat;\n ahci_check_irq(s);\n }\n \n@@ -718,7 +745,7 @@ static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs)\n \n /* Trigger IRQ if interrupt bit is set (which currently, it always is) */\n if (sdb_fis->flags & 0x40) {\n- ahci_trigger_irq(s, ad, PORT_IRQ_SDB_FIS);\n+ ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS);\n }\n }\n \n@@ -761,10 +788,10 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len)\n ad->port.ifs[0].status;\n \n if (pio_fis[2] & ERR_STAT) {\n- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);\n+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);\n }\n \n- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_PIOS_FIS);\n+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_PSS);\n }\n \n static bool ahci_write_fis_d2h(AHCIDevice *ad)\n@@ -804,10 +831,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad)\n ad->port.ifs[0].status;\n \n if (d2h_fis[2] & ERR_STAT) {\n- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_TF_ERR);\n+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES);\n }\n \n- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_D2H_REG_FIS);\n+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS);\n return true;\n }\n \n@@ -1082,7 +1109,7 @@ static void process_ncq_command(AHCIState *s, int port, uint8_t *cmd_fis,\n \"is smaller than the requested size (0x%zx)\",\n ncq_tfs->sglist.size, size);\n ncq_err(ncq_tfs);\n- ahci_trigger_irq(ad->hba, ad, PORT_IRQ_OVERFLOW);\n+ ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_OFS);\n return;\n } else if (ncq_tfs->sglist.size != size) {\n trace_process_ncq_command_large(s, port, tag,\n@@ -1225,7 +1252,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot)\n trace_handle_cmd_badfis(s, port);\n return -1;\n } else if (cmd_len != 0x80) {\n- ahci_trigger_irq(s, &s->dev[port], PORT_IRQ_HBUS_ERR);\n+ ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS);\n trace_handle_cmd_badmap(s, port, cmd_len);\n goto out;\n }\ndiff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h\nindex 1e21169..ce2e818 100644\n--- a/hw/ide/ahci_internal.h\n+++ b/hw/ide/ahci_internal.h\n@@ -91,6 +91,31 @@\n #define PORT_CMD_ISSUE 0x38 /* command issue */\n #define PORT_RESERVED 0x3c /* reserved */\n \n+/* Port interrupt bit descriptors */\n+enum AHCIPortIRQ {\n+ AHCI_PORT_IRQ_BIT_DHRS = 0,\n+ AHCI_PORT_IRQ_BIT_PSS = 1,\n+ AHCI_PORT_IRQ_BIT_DSS = 2,\n+ AHCI_PORT_IRQ_BIT_SDBS = 3,\n+ AHCI_PORT_IRQ_BIT_UFS = 4,\n+ AHCI_PORT_IRQ_BIT_DPS = 5,\n+ AHCI_PORT_IRQ_BIT_PCS = 6,\n+ AHCI_PORT_IRQ_BIT_DMPS = 7,\n+ /* RESERVED */\n+ AHCI_PORT_IRQ_BIT_PRCS = 22,\n+ AHCI_PORT_IRQ_BIT_IPMS = 23,\n+ AHCI_PORT_IRQ_BIT_OFS = 24,\n+ /* RESERVED */\n+ AHCI_PORT_IRQ_BIT_INFS = 26,\n+ AHCI_PORT_IRQ_BIT_IFS = 27,\n+ AHCI_PORT_IRQ_BIT_HBDS = 28,\n+ AHCI_PORT_IRQ_BIT_HBFS = 29,\n+ AHCI_PORT_IRQ_BIT_TFES = 30,\n+ AHCI_PORT_IRQ_BIT_CPDS = 31,\n+ AHCI_PORT_IRQ__COUNT = 32\n+};\n+\n+\n /* PORT_IRQ_{STAT,MASK} bits */\n #define PORT_IRQ_COLD_PRES (1U << 31) /* cold presence detect */\n #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */\n@@ -98,18 +123,19 @@\n #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */\n #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */\n #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */\n+ /* reserved */\n #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */\n #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */\n-\n #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */\n-#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */\n-#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */\n-#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */\n-#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */\n-#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */\n-#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */\n-#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */\n-#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */\n+ /* reserved */\n+#define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */\n+#define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */\n+#define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */\n+#define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */\n+#define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */\n+#define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */\n+#define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */\n+#define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */\n \n #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \\\n PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \\\ndiff --git a/hw/ide/trace-events b/hw/ide/trace-events\nindex 0b61c5d..e15fd77 100644\n--- a/hw/ide/trace-events\n+++ b/hw/ide/trace-events\n@@ -62,7 +62,7 @@ ahci_port_read(void *s, int port, int offset, uint32_t ret) \"ahci(%p)[%d]: port\n ahci_irq_raise(void *s) \"ahci(%p): raise irq\"\n ahci_irq_lower(void *s) \"ahci(%p): lower irq\"\n ahci_check_irq(void *s, uint32_t old, uint32_t new) \"ahci(%p): check irq 0x%08x --> 0x%08x\"\n-\n+ahci_trigger_irq(void *s, int port, const char *name, uint32_t val, uint32_t old, uint32_t new, uint32_t effective) \"ahci(%p)[%d]: trigger irq +%s (0x%08x); irqstat: 0x%08x --> 0x%08x; effective: 0x%08x\"\n ahci_port_write(void *s, int port, int offset, uint32_t val) \"ahci(%p)[%d]: port write @ 0x%x: 0x%08x\"\n ahci_mem_read_32(void *s, uint64_t addr, uint32_t val) \"ahci(%p): mem read @ 0x%\"PRIx64\": 0x%08x\"\n ahci_mem_read(void *s, unsigned size, uint64_t addr, uint64_t val) \"ahci(%p): read%u @ 0x%\"PRIx64\": 0x%016\"PRIx64\n","prefixes":["v3","7/9"]}