{"id":808480,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808480/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<20170831235123.GA5644@fergus.ozlabs.ibm.com>","date":"2017-08-31T23:51:23","name":"[19/17] powerpc: Wrap register number correctly for string load/store instructions","commit_ref":"45f62159f3aafe27e2df45a3ec83b32ca7304410","pull_url":null,"state":"accepted","archived":false,"hash":"9829530589c18741eef88a5072e7a7154fdfe246","submitter":{"id":67079,"url":"http://patchwork.ozlabs.org/api/1.0/people/67079/?format=json","name":"Paul Mackerras","email":"paulus@ozlabs.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170831235123.GA5644@fergus.ozlabs.ibm.com/mbox/","series":[{"id":522,"url":"http://patchwork.ozlabs.org/api/1.0/series/522/?format=json","date":"2017-08-30T04:12:25","name":"powerpc: Do alignment fixups using analyse_instr etc.","version":3,"mbox":"http://patchwork.ozlabs.org/series/522/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808480/checks/","tags":{},"headers":{"Return-Path":"<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjzhV22Wjz9s7p\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri,  1 Sep 2017 09:52:58 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xjzhV0w5JzDqfx\n\tfor <patchwork-incoming@ozlabs.org>;\n\tFri,  1 Sep 2017 09:52:58 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xjzfn1XqwzDqYs\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri,  1 Sep 2017 09:51:29 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xjzfn0z2qz9s7p; Fri,  1 Sep 2017 09:51:29 +1000 (AEST)","by ozlabs.org (Postfix, from userid 1003)\n\tid 3xjzfn0Mvtz9s8J; Fri,  1 Sep 2017 09:51:28 +1000 (AEST)"],"Authentication-Results":["ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"cRZ2mReT\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"cRZ2mReT\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"cRZ2mReT\"; \n\tdkim-atps=neutral"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504223489; bh=VXn/uK7buypKRdc/1fSzK18EQume6GQDsf3mCAHYWu4=;\n\th=Date:From:To:Subject:References:In-Reply-To:From;\n\tb=cRZ2mReTf4+5GUYIfwCu4gerKxVQ3HMI8C1vAaztZoet8UmNt1eBbFt4fGscLV1D7\n\t2lYhRNmfvrsj/yYN6rleX85Sl/n2BIASSwz67PDHTi6VnJyGq6pRDDfpQwWIGW+3Za\n\tzHrQTEPacL2TB+6hUdSkiOEbOw0DMgn9Hd6zKhNpBArAmjRFcuAKDTt+f5hPsOW4bs\n\tsQH3M1V5OOCtrit6KEeW9FEfma11fH7nTIjsjEibMxAqhBkomOjObWbG0PsP0r5NPZ\n\tOIG+Yn5AXfVZfOD1Eu/zrYL8xugB8wUbAdA0iz5Ea5sd0Kr8hUkEuAT5cAsRwcBU6s\n\tU+s3vEwZ3OXwQ==","Date":"Fri, 1 Sep 2017 09:51:23 +1000","From":"Paul Mackerras <paulus@ozlabs.org>","To":"linuxppc-dev@ozlabs.org","Subject":"[PATCH 19/17] powerpc: Wrap register number correctly for string\n\tload/store instructions","Message-ID":"<20170831235123.GA5644@fergus.ozlabs.ibm.com>","References":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","User-Agent":"Mutt/1.5.24 (2015-08-30)","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>","List-Unsubscribe":"<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>","List-Archive":"<http://lists.ozlabs.org/pipermail/linuxppc-dev/>","List-Post":"<mailto:linuxppc-dev@lists.ozlabs.org>","List-Help":"<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>","List-Subscribe":"<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>"},"content":"Michael Ellerman reported that emulate_loadstore() was trying to\naccess element 32 of regs->gpr[], which doesn't exist, when\nemulating a string store instruction.  This is because the string\nload and store instructions (lswi, lswx, stswi and stswx) are\ndefined to wrap around from register 31 to register 0 if the number\nof bytes being loaded or stored is sufficiently large.  This wrapping\nwas not implemented in the emulation code.  To fix it, we mask the\nregister number after incrementing it.\n\nReported-by: Michael Ellerman <mpe@ellerman.id.au>\nFixes: c9f6f4ed95d4 (\"powerpc: Implement emulation of string loads and stores\")\nSigned-off-by: Paul Mackerras <paulus@ozlabs.org>\n---\n arch/powerpc/lib/sstep.c | 6 ++++--\n 1 file changed, 4 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 2f6897c..c406611 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -2865,7 +2865,8 @@ int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)\n \t\t\t\tv32 = byterev_4(v32);\n \t\t\tregs->gpr[rd] = v32;\n \t\t\tea += 4;\n-\t\t\t++rd;\n+\t\t\t/* reg number wraps from 31 to 0 for lsw[ix] */\n+\t\t\trd = (rd + 1) & 0x1f;\n \t\t}\n \t\tbreak;\n \n@@ -2934,7 +2935,8 @@ int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)\n \t\t\tif (err)\n \t\t\t\tbreak;\n \t\t\tea += 4;\n-\t\t\t++rd;\n+\t\t\t/* reg number wraps from 31 to 0 for stsw[ix] */\n+\t\t\trd = (rd + 1) & 0x1f;\n \t\t}\n \t\tbreak;\n \n","prefixes":["19/17"]}