{"id":808344,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808344/?format=json","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.0/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<1504198860-12951-26-git-send-email-Dave.Martin@arm.com>","date":"2017-08-31T17:00:57","name":"[v2,25/28] arm64/sve: Detect SVE and activate runtime support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0702cc78aa21c03f77dd0bfc6fff08445d53652d","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.0/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-26-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":882,"url":"http://patchwork.ozlabs.org/api/1.0/series/882/?format=json","date":"2017-08-31T17:00:32","name":"ARM Scalable Vector Extension (SVE)","version":2,"mbox":"http://patchwork.ozlabs.org/series/882/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808344/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83980-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"L4GNFQ9N\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpdw5mJ6z9sD5\n\tfor ;\n\tFri, 1 Sep 2017 03:05:08 +1000 (AEST)","(qmail 85461 invoked by alias); 31 Aug 2017 17:02:16 -0000","(qmail 85408 invoked by uid 89); 31 Aug 2017 17:02:16 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; q=dns; s=default; b=ozD7yRAyJYaa/m5UJAnXappaLy50iqL\n\tqkL8fJ3N/DP+X1Gp8nqqZZ9WPnEFOm6irxAh7rhaaiyErvjkzGcUu3eLYSFYujAo\n\tcSnJDeIUN5ilhqJWbC6FBtcH2V85NgrsuBLh002CUVFlo3EypUaP8ynyIuOgBTc+\n\tKMbvFlcopVc0=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references; s=default; bh=6P/DEvfwSjkJH+2u+snQyFFCZgA=; b=L4GNF\n\tQ9NAmr8IXQelX5IYrXHSAhpPNbzBZct72tXO0YA5zAWCcNr5vqilMo7RVNoAPDnU\n\tL7q/HKTPrV5D0/7g+TUaegboFZJtexVz3z51zDVDCI69gQTugmchgBbk6ZjB1Vwb\n\tEj8EStZWR45s0mtMZ0gagZW4cisvIpGwUsoo6I=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.1 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS,\n\tRP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=exposure","X-HELO":"foss.arm.com","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Cc":"Catalin Marinas , Will Deacon\n\t, \tArd Biesheuvel ,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= ,\n\tSzabolcs Nagy , Richard Sandiford\n\t, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org","Subject":"[PATCH v2 25/28] arm64/sve: Detect SVE and activate runtime support","Date":"Thu, 31 Aug 2017 18:00:57 +0100","Message-Id":"<1504198860-12951-26-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>"},"content":"This patch enables detection of hardware SVE support via the\ncpufeatures framework, and reports its presence to the kernel and\nuserspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap\nrespectively.\n\nUserspace can also detect SVE using ID_AA64PFR0_EL1, using the\ncpufeatures MRS emulation.\n\nWhen running on hardware that supports SVE, this enables runtime\nkernel support for SVE, and allows user tasks to execute SVE\ninstructions and make of the of the SVE-specific user/kernel\ninterface extensions implemented by this series.\n\nSigned-off-by: Dave Martin \nReviewed-by: Suzuki K Poulose \n\n---\n\nChanges since v1\n----------------\n\nRequested by Suzuki Poulose:\n\n* Update CPUID documentation to document exposure of SVE field.\n\n* Applied deferred Reviewed-by dependent on the above change.\n---\n Documentation/arm64/cpu-feature-registers.txt | 6 +++++-\n arch/arm64/include/asm/cpucaps.h | 3 ++-\n arch/arm64/include/asm/cpufeature.h | 3 ++-\n arch/arm64/include/uapi/asm/hwcap.h | 1 +\n arch/arm64/kernel/cpufeature.c | 16 ++++++++++++++++\n arch/arm64/kernel/cpuinfo.c | 1 +\n 6 files changed, 27 insertions(+), 3 deletions(-)","diff":"diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt\nindex dad411d..d65504c 100644\n--- a/Documentation/arm64/cpu-feature-registers.txt\n+++ b/Documentation/arm64/cpu-feature-registers.txt\n@@ -132,7 +132,11 @@ infrastructure:\n x--------------------------------------------------x\n | Name | bits | visible |\n |--------------------------------------------------|\n- | RES0 | [63-28] | n |\n+ | RES0 | [63-36] | n |\n+ |--------------------------------------------------|\n+ | SVE | [35-32] | y |\n+ |--------------------------------------------------|\n+ | RES0 | [31-28] | n |\n |--------------------------------------------------|\n | GIC | [27-24] | n |\n |--------------------------------------------------|\ndiff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h\nindex 8da6216..2ff7c5e 100644\n--- a/arch/arm64/include/asm/cpucaps.h\n+++ b/arch/arm64/include/asm/cpucaps.h\n@@ -40,7 +40,8 @@\n #define ARM64_WORKAROUND_858921\t\t\t19\n #define ARM64_WORKAROUND_CAVIUM_30115\t\t20\n #define ARM64_HAS_DCPOP\t\t\t\t21\n+#define ARM64_SVE\t\t\t\t22\n \n-#define ARM64_NCAPS\t\t\t\t22\n+#define ARM64_NCAPS\t\t\t\t23\n \n #endif /* __ASM_CPUCAPS_H */\ndiff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h\nindex d98e7ba..bc987eb 100644\n--- a/arch/arm64/include/asm/cpufeature.h\n+++ b/arch/arm64/include/asm/cpufeature.h\n@@ -273,7 +273,8 @@ static inline bool system_uses_ttbr0_pan(void)\n \n static inline bool system_supports_sve(void)\n {\n-\treturn false;\n+\treturn IS_ENABLED(CONFIG_ARM64_SVE) &&\n+\t\tcpus_have_const_cap(ARM64_SVE);\n }\n \n /*\ndiff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h\nindex 4b9344c..c6e1e45 100644\n--- a/arch/arm64/include/uapi/asm/hwcap.h\n+++ b/arch/arm64/include/uapi/asm/hwcap.h\n@@ -36,5 +36,6 @@\n #define HWCAP_FCMA\t\t(1 << 14)\n #define HWCAP_LRCPC\t\t(1 << 15)\n #define HWCAP_DCPOP\t\t(1 << 16)\n+#define HWCAP_SVE\t\t(1 << 17)\n \n #endif /* _UAPI__ASM_HWCAP_H */\ndiff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c\nindex c30bb6b..3e74d93 100644\n--- a/arch/arm64/kernel/cpufeature.c\n+++ b/arch/arm64/kernel/cpufeature.c\n@@ -141,6 +141,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {\n };\n \n static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {\n+\tARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),\n \tARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64PFR0_GIC_SHIFT, 4, 0),\n \tS_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),\n \tS_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),\n@@ -942,6 +943,18 @@ static const struct arm64_cpu_capabilities arm64_features[] = {\n \t\t.min_field_value = 1,\n \t},\n #endif\n+#ifdef CONFIG_ARM64_SVE\n+\t{\n+\t\t.desc = \"Scalable Vector Extension\",\n+\t\t.capability = ARM64_SVE,\n+\t\t.def_scope = SCOPE_SYSTEM,\n+\t\t.sys_reg = SYS_ID_AA64PFR0_EL1,\n+\t\t.sign = FTR_UNSIGNED,\n+\t\t.field_pos = ID_AA64PFR0_SVE_SHIFT,\n+\t\t.min_field_value = ID_AA64PFR0_SVE,\n+\t\t.matches = has_cpuid_feature,\n+\t},\n+#endif /* CONFIG_ARM64_SVE */\n \t{},\n };\n \n@@ -974,6 +987,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {\n \tHWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),\n \tHWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),\n \tHWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),\n+#ifdef CONFIG_ARM64_SVE\n+\tHWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),\n+#endif\n \t{},\n };\n \ndiff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c\nindex be260e8..9559dde 100644\n--- a/arch/arm64/kernel/cpuinfo.c\n+++ b/arch/arm64/kernel/cpuinfo.c\n@@ -70,6 +70,7 @@ static const char *const hwcap_str[] = {\n \t\"fcma\",\n \t\"lrcpc\",\n \t\"dcpop\",\n+\t\"sve\",\n \tNULL\n };\n \n","prefixes":["v2","25/28"]}