{"id":808331,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808331/?format=json","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.0/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<1504198860-12951-13-git-send-email-Dave.Martin@arm.com>","date":"2017-08-31T17:00:44","name":"[v2,12/28] arm64/sve: Support vector length resetting for new processes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"88b4ce05587340e850ba1a6a3f1ef60f0fb84c93","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.0/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-13-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":882,"url":"http://patchwork.ozlabs.org/api/1.0/series/882/?format=json","date":"2017-08-31T17:00:32","name":"ARM Scalable Vector Extension (SVE)","version":2,"mbox":"http://patchwork.ozlabs.org/series/882/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808331/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83971-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"Q1aEgyVG\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpbs4Pbnz9s81\n\tfor ;\n\tFri, 1 Sep 2017 03:03:21 +1000 (AEST)","(qmail 81643 invoked by alias); 31 Aug 2017 17:01:53 -0000","(qmail 81588 invoked by uid 89); 31 Aug 2017 17:01:52 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=WbRNeiG7jHqRy0rmWSO6ZXnheko8ELr3SV5LeSMoWQM\n\tlYDdf9goD9fvPcT8n3UH020wGhLXczngf2hiw9zRY/cymBAXte+bTjsGkfJ98xGy\n\tLBqj4Hq4u70fWykuQiyV0Yk7x33nt2PYcduBJgoYUAoe0Y5/4d1C45wkuzRt438w\n\t=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=/SxxZGGyDJi28Ha0QPuXIPbRyNU=; b=Q1aEgyVGdMfDgMSGg\n\tmfpAVtDZWQJXflmna9iDrEphLRoqnvR+EIO+p4w1ZCkGgVJLU1dqTBs7REKUqdGa\n\tONzxtZF2pOHS6S2TTVggjTDCp5g1TFf7RAaSsLvqzbNL5cZBkPuYGrfKibzLpi6x\n\tPEPQHhqOwBKdvndNum6QyWhhUw=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"","List-Unsubscribe":"","List-Subscribe":"","List-Archive":"","List-Post":"","List-Help":",\n\t","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=","X-HELO":"foss.arm.com","From":"Dave Martin ","To":"linux-arm-kernel@lists.infradead.org","Cc":"Catalin Marinas , Will Deacon\n\t, \tArd Biesheuvel ,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= ,\n\tSzabolcs Nagy , Richard Sandiford\n\t, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org","Subject":"[PATCH v2 12/28] arm64/sve: Support vector length resetting for new\n\tprocesses","Date":"Thu, 31 Aug 2017 18:00:44 +0100","Message-Id":"<1504198860-12951-13-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"It's desirable to be able to reset the vector length to some sane\ndefault for new processes, since the new binary and its libraries\nprocesses may or may not be SVE-aware.\n\nThis patch tracks the desired post-exec vector length (if any) in a\nnew thread member sve_vl_onexec, and adds a new thread flag\nTIF_SVE_VL_INHERIT to control whether to inherit or reset the\nvector length. Currently these are inactive. Subsequent patches\nwill provide the capability to configure them.\n\nSigned-off-by: Dave Martin \nCc: Alex Bennée \n\n---\n\nChanges since v1\n----------------\n\nRequested by Alex Bennée:\n\n* Make sve_vl_onexec an unsigned int: that's the type used virtually\neverywhere else, and the memory saving is too minor to be interesting.\n---\n arch/arm64/include/asm/processor.h | 1 +\n arch/arm64/include/asm/thread_info.h | 1 +\n arch/arm64/kernel/fpsimd.c | 16 ++++++++++++----\n 3 files changed, 14 insertions(+), 4 deletions(-)","diff":"diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h\nindex 4831d28..3faceac 100644\n--- a/arch/arm64/include/asm/processor.h\n+++ b/arch/arm64/include/asm/processor.h\n@@ -87,6 +87,7 @@ struct thread_struct {\n \tstruct fpsimd_state\tfpsimd_state;\n \tvoid\t\t\t*sve_state;\t/* SVE registers, if any */\n \tunsigned int\t\tsve_vl;\t\t/* SVE vector length */\n+\tunsigned int\t\tsve_vl_onexec;\t/* SVE vl after next exec */\n \tunsigned long\t\tfault_address;\t/* fault info */\n \tunsigned long\t\tfault_code;\t/* ESR_EL1 value */\n \tstruct debug_info\tdebug;\t\t/* debugging */\ndiff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h\nindex f0880fc..d3568ab 100644\n--- a/arch/arm64/include/asm/thread_info.h\n+++ b/arch/arm64/include/asm/thread_info.h\n@@ -92,6 +92,7 @@ void arch_setup_new_exec(void);\n #define TIF_SINGLESTEP\t\t21\n #define TIF_32BIT\t\t22\t/* 32bit process */\n #define TIF_SVE\t\t\t23\t/* Scalable Vector Extension in use */\n+#define TIF_SVE_VL_INHERIT\t24\t/* Inherit sve_vl_onexec across exec */\n \n #define _TIF_SIGPENDING\t\t(1 << TIF_SIGPENDING)\n #define _TIF_NEED_RESCHED\t(1 << TIF_NEED_RESCHED)\ndiff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c\nindex 9b1ebd7..e20b44d 100644\n--- a/arch/arm64/kernel/fpsimd.c\n+++ b/arch/arm64/kernel/fpsimd.c\n@@ -106,6 +106,9 @@\n */\n static DEFINE_PER_CPU(struct fpsimd_state *, fpsimd_last_state);\n \n+/* Default VL for tasks that don't set it explicitly: */\n+static int sve_default_vl = SVE_VL_MIN;\n+\n static void sve_free(struct task_struct *task)\n {\n \tkfree(task->thread.sve_state);\n@@ -380,15 +383,20 @@ void fpsimd_flush_thread(void)\n \t\t * If a bug causes this to go wrong, we make some noise and\n \t\t * try to fudge thread.sve_vl to a safe value here.\n \t\t */\n-\t\tvl = current->thread.sve_vl;\n-\n-\t\tif (vl == 0)\n-\t\t\tvl = SVE_VL_MIN;\n+\t\tvl = current->thread.sve_vl_onexec ?\n+\t\t\tcurrent->thread.sve_vl_onexec : sve_default_vl;\n \n \t\tif (WARN_ON(!sve_vl_valid(vl)))\n \t\t\tvl = SVE_VL_MIN;\n \n \t\tcurrent->thread.sve_vl = vl;\n+\n+\t\t/*\n+\t\t * If the task is not set to inherit, ensure that the vector\n+\t\t * length will be reset by a subsequent exec:\n+\t\t */\n+\t\tif (!test_thread_flag(TIF_SVE_VL_INHERIT))\n+\t\t\tcurrent->thread.sve_vl_onexec = 0;\n \t}\n \n \tset_thread_flag(TIF_FOREIGN_FPSTATE);\n","prefixes":["v2","12/28"]}