{"id":808327,"url":"http://patchwork.ozlabs.org/api/1.0/patches/808327/?format=json","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.0/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<1504198860-12951-9-git-send-email-Dave.Martin@arm.com>","date":"2017-08-31T17:00:40","name":"[v2,08/28] arm64/sve: Kconfig update and conditional compilation support","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"42c8337c1e7de7d336dfcb750d923ee44b5e906b","submitter":{"id":26612,"url":"http://patchwork.ozlabs.org/api/1.0/people/26612/?format=json","name":"Dave Martin","email":"Dave.Martin@arm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1504198860-12951-9-git-send-email-Dave.Martin@arm.com/mbox/","series":[{"id":882,"url":"http://patchwork.ozlabs.org/api/1.0/series/882/?format=json","date":"2017-08-31T17:00:32","name":"ARM Scalable Vector Extension (SVE)","version":2,"mbox":"http://patchwork.ozlabs.org/series/882/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808327/checks/","tags":{},"headers":{"Return-Path":"<libc-alpha-return-83967-incoming=patchwork.ozlabs.org@sourceware.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=libc-alpha-return-83967-incoming=patchwork.ozlabs.org@sourceware.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tsecure) header.d=sourceware.org header.i=@sourceware.org\n\theader.b=\"xyl1nvK8\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjpZr4QF4z9sPt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri,  1 Sep 2017 03:02:28 +1000 (AEST)","(qmail 80006 invoked by alias); 31 Aug 2017 17:01:42 -0000","(qmail 79881 invoked by uid 89); 31 Aug 2017 17:01:41 -0000"],"DomainKey-Signature":"a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\tq=dns; s=default; b=PzXeAo4vUFnh6DpNRcu8miYZCho86jQTW/7GXK24tRM\n\tCaUV+ZUgYFwGoOV1q5VMmqRMY9ZFY5FVXpkD5WdKMlU1l+CEIHggnZspSPGY814B\n\tfqi1CZkcg2KMulvo66Pz3OtJ8ybQTEKYA9olFSsMNlu/gW4jKyUaOcw9ZA9s6/i4\n\t=","DKIM-Signature":"v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id\n\t:list-unsubscribe:list-subscribe:list-archive:list-post\n\t:list-help:sender:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-type:content-transfer-encoding;\n\ts=default; bh=RnjmfE53UMuDpb4Mp6mUrl+INxE=; b=xyl1nvK8Gk+1cRgWk\n\t7ynqWgE+ilzpNPtz8HeV/4aNZTeHhZdnalFg5kFi9c2T75bkdfSZd68OcJFbJwS+\n\tZWfRyEu2ahv3FPlATwUXmA2Unb0cq5CIOmCa9X3qIyP7smMaAGc+gxF1b9AUEwnQ\n\tNY9Jw4OatDLHlpy1tsba2rgHtg=","Mailing-List":"contact libc-alpha-help@sourceware.org; run by ezmlm","Precedence":"bulk","List-Id":"<libc-alpha.sourceware.org>","List-Unsubscribe":"<mailto:libc-alpha-unsubscribe-incoming=patchwork.ozlabs.org@sourceware.org>","List-Subscribe":"<mailto:libc-alpha-subscribe@sourceware.org>","List-Archive":"<http://sourceware.org/ml/libc-alpha/>","List-Post":"<mailto:libc-alpha@sourceware.org>","List-Help":"<mailto:libc-alpha-help@sourceware.org>,\n\t<http://sourceware.org/ml/#faqs>","Sender":"libc-alpha-owner@sourceware.org","X-Virus-Found":"No","X-Spam-SWARE-Status":"No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n\tGIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD,\n\tSPF_PASS autolearn=ham version=3.3.2 spammy=Hx-languages-length:1731","X-HELO":"foss.arm.com","From":"Dave Martin <Dave.Martin@arm.com>","To":"linux-arm-kernel@lists.infradead.org","Cc":"Catalin Marinas <catalin.marinas@arm.com>, Will Deacon\n\t<will.deacon@arm.com>, \tArd Biesheuvel <ard.biesheuvel@linaro.org>,\n\t=?utf-8?q?Alex_Benn=C3=A9?= =?utf-8?q?e?= <alex.bennee@linaro.org>,\n\tSzabolcs Nagy <szabolcs.nagy@arm.com>, Richard Sandiford\n\t<richard.sandiford@arm.com>, \tkvmarm@lists.cs.columbia.edu,\n\tlibc-alpha@sourceware.org, \tlinux-arch@vger.kernel.org","Subject":"[PATCH v2 08/28] arm64/sve: Kconfig update and conditional\n\tcompilation support","Date":"Thu, 31 Aug 2017 18:00:40 +0100","Message-Id":"<1504198860-12951-9-git-send-email-Dave.Martin@arm.com>","In-Reply-To":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>","References":"<1504198860-12951-1-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit"},"content":"This patch adds CONFIG_ARM64_SVE to control building of SVE support\ninto the kernel, and adds a stub predicate system_supports_sve() to\ncontrol conditional compilation and runtime SVE support.\n\nsystem_supports_sve() just returns false for now: it will be\nreplaced with a non-trivial implementation in a later patch, once\nSVE support is complete enough to be enabled safely.\n\nSigned-off-by: Dave Martin <Dave.Martin@arm.com>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\n---\n arch/arm64/Kconfig                  | 11 +++++++++++\n arch/arm64/include/asm/cpufeature.h |  5 +++++\n 2 files changed, 16 insertions(+)","diff":"diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig\nindex ca711ac..9b3a50e 100644\n--- a/arch/arm64/Kconfig\n+++ b/arch/arm64/Kconfig\n@@ -975,6 +975,17 @@ config ARM64_PMEM\n \n endmenu\n \n+config ARM64_SVE\n+\tbool \"ARM Scalable Vector Extension support\"\n+\tdefault y\n+\thelp\n+\t  The Scalable Vector Extension (SVE) is an extension to the AArch64\n+\t  execution state which complements and extends the SIMD functionality\n+\t  of the base architecture to support much larger vectors and to enable\n+\t  additional vectorisation opportunities.\n+\n+\t  To enable use of this extension on CPUs that implement it, say Y.\n+\n config ARM64_MODULE_CMODEL_LARGE\n \tbool\n \ndiff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h\nindex 428ee1f..4ea3441 100644\n--- a/arch/arm64/include/asm/cpufeature.h\n+++ b/arch/arm64/include/asm/cpufeature.h\n@@ -262,6 +262,11 @@ static inline bool system_uses_ttbr0_pan(void)\n \t\t!cpus_have_const_cap(ARM64_HAS_PAN);\n }\n \n+static inline bool system_supports_sve(void)\n+{\n+\treturn false;\n+}\n+\n #endif /* __ASSEMBLY__ */\n \n #endif\n","prefixes":["v2","08/28"]}