{"id":807880,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807880/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<20170830194617.26621-7-clg@kaod.org>","date":"2017-08-30T19:46:15","name":"[v3,6/8] powerpc/xive: introduce H_INT_ESB hcall","commit_ref":"bed81ee181dd6b21171cffbb80472cc5b774c24d","pull_url":null,"state":"accepted","archived":false,"hash":"5b3ced523c91919eb6e84e7c5631867a9f810b0e","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/1.0/people/68548/?format=json","name":"Cédric Le Goater","email":"clg@kaod.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170830194617.26621-7-clg@kaod.org/mbox/","series":[{"id":695,"url":"http://patchwork.ozlabs.org/api/1.0/series/695/?format=json","date":"2017-08-30T19:46:17","name":"guest exploitation of the XIVE interrupt controller","version":3,"mbox":"http://patchwork.ozlabs.org/series/695/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807880/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xjGZn2pb9z9sN7\n\tfor ;\n\tThu, 31 Aug 2017 06:00:33 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xjGZn21wlzDqgp\n\tfor ;\n\tThu, 31 Aug 2017 06:00:33 +1000 (AEST)","from 2.mo68.mail-out.ovh.net (2.mo68.mail-out.ovh.net\n\t[46.105.52.162])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xjGTv2m2SzDqTr\n\tfor ;\n\tThu, 31 Aug 2017 05:56:19 +1000 (AEST)","from player776.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo68.mail-out.ovh.net (Postfix) with ESMTP id 9DC1F775E2\n\tfor ;\n\tWed, 30 Aug 2017 21:47:10 +0200 (CEST)","from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: clg@kaod.org)\n\tby player776.ha.ovh.net (Postfix) with ESMTPSA id 72CE340006E;\n\tWed, 30 Aug 2017 21:47:04 +0200 (CEST)"],"X-Greylist":"delayed 558 seconds by postgrey-1.36 at bilbo;\n\tThu, 31 Aug 2017 05:56:19 AEST","From":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","To":"linuxppc-dev@lists.ozlabs.org","Subject":"[PATCH v3 6/8] powerpc/xive: introduce H_INT_ESB hcall","Date":"Wed, 30 Aug 2017 21:46:15 +0200","Message-Id":"<20170830194617.26621-7-clg@kaod.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170830194617.26621-1-clg@kaod.org>","References":"<20170830194617.26621-1-clg@kaod.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-Ovh-Tracer-Id":"1602718520993811389","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrudeigddugedtucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"David Gibson , Paul Mackerras\n\t, =?utf-8?q?C=C3=A9dric_Le_Goater?= ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"The H_INT_ESB hcall() is used to issue a load or store to the ESB page\ninstead of using the MMIO pages. This can be used as a workaround on\nsome HW issues. The OS knows that this hcall should be used on an\ninterrupt source when the ESB hcall flag is set to 1 in the hcall\nH_INT_GET_SOURCE_INFO.\n\nTo maintain the frontier between the xive frontend and backend, we\nintroduce a new xive operation 'esb_rw' to be used in the routines\ndoing memory accesses on the ESBs.\n\nSigned-off-by: Cédric Le Goater \n---\n arch/powerpc/include/asm/xive.h | 1 +\n arch/powerpc/sysdev/xive/common.c | 10 ++++++--\n arch/powerpc/sysdev/xive/spapr.c | 44 +++++++++++++++++++++++++++++++-\n arch/powerpc/sysdev/xive/xive-internal.h | 1 +\n 4 files changed, 53 insertions(+), 3 deletions(-)","diff":"diff --git a/arch/powerpc/include/asm/xive.h b/arch/powerpc/include/asm/xive.h\nindex 64ec9bbcf03e..371fbebf1ec9 100644\n--- a/arch/powerpc/include/asm/xive.h\n+++ b/arch/powerpc/include/asm/xive.h\n@@ -56,6 +56,7 @@ struct xive_irq_data {\n #define XIVE_IRQ_FLAG_SHIFT_BUG\t0x04\n #define XIVE_IRQ_FLAG_MASK_FW\t0x08\n #define XIVE_IRQ_FLAG_EOI_FW\t0x10\n+#define XIVE_IRQ_FLAG_H_INT_ESB\t0x20\n \n #define XIVE_INVALID_CHIP_ID\t-1\n \ndiff --git a/arch/powerpc/sysdev/xive/common.c b/arch/powerpc/sysdev/xive/common.c\nindex ac5f18a66742..8fd58773c241 100644\n--- a/arch/powerpc/sysdev/xive/common.c\n+++ b/arch/powerpc/sysdev/xive/common.c\n@@ -198,7 +198,10 @@ static u8 xive_esb_read(struct xive_irq_data *xd, u32 offset)\n \tif (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)\n \t\toffset |= offset << 4;\n \n-\tval = in_be64(xd->eoi_mmio + offset);\n+\tif ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)\n+\t\tval = xive_ops->esb_rw(xd->hw_irq, offset, 0, 0);\n+\telse\n+\t\tval = in_be64(xd->eoi_mmio + offset);\n \n \treturn (u8)val;\n }\n@@ -209,7 +212,10 @@ static void xive_esb_write(struct xive_irq_data *xd, u32 offset, u64 data)\n \tif (xd->flags & XIVE_IRQ_FLAG_SHIFT_BUG)\n \t\toffset |= offset << 4;\n \n-\tout_be64(xd->eoi_mmio + offset, data);\n+\tif ((xd->flags & XIVE_IRQ_FLAG_H_INT_ESB) && xive_ops->esb_rw)\n+\t\txive_ops->esb_rw(xd->hw_irq, offset, data, 1);\n+\telse\n+\t\tout_be64(xd->eoi_mmio + offset, data);\n }\n \n #ifdef CONFIG_XMON\ndiff --git a/arch/powerpc/sysdev/xive/spapr.c b/arch/powerpc/sysdev/xive/spapr.c\nindex 0fcae7504353..43e9eeb0d39f 100644\n--- a/arch/powerpc/sysdev/xive/spapr.c\n+++ b/arch/powerpc/sysdev/xive/spapr.c\n@@ -224,7 +224,46 @@ static long plpar_int_sync(unsigned long flags, unsigned long lisn)\n \treturn 0;\n }\n \n-#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60)) /* TODO */\n+#define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))\n+\n+static long plpar_int_esb(unsigned long flags,\n+\t\t\t unsigned long lisn,\n+\t\t\t unsigned long offset,\n+\t\t\t unsigned long in_data,\n+\t\t\t unsigned long *out_data)\n+{\n+\tunsigned long retbuf[PLPAR_HCALL_BUFSIZE];\n+\tlong rc;\n+\n+\tpr_devel(\"H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\\n\",\n+\t\tflags, lisn, offset, in_data);\n+\n+\trc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset, in_data);\n+\tif (rc) {\n+\t\tpr_err(\"H_INT_ESB lisn=%ld offset=%ld returned %ld\\n\",\n+\t\t lisn, offset, rc);\n+\t\treturn rc;\n+\t}\n+\n+\t*out_data = retbuf[0];\n+\n+\treturn 0;\n+}\n+\n+static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)\n+{\n+\tunsigned long read_data;\n+\tlong rc;\n+\n+\trc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,\n+\t\t\t lisn, offset, data, &read_data);\n+\tif (rc)\n+\t\treturn -1;\n+\n+\treturn write ? 0 : read_data;\n+}\n+\n+#define XIVE_SRC_H_INT_ESB (1ull << (63 - 60))\n #define XIVE_SRC_LSI (1ull << (63 - 61))\n #define XIVE_SRC_TRIGGER (1ull << (63 - 62))\n #define XIVE_SRC_STORE_EOI (1ull << (63 - 63))\n@@ -244,6 +283,8 @@ static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)\n \tif (rc)\n \t\treturn -EINVAL;\n \n+\tif (flags & XIVE_SRC_H_INT_ESB)\n+\t\tdata->flags |= XIVE_IRQ_FLAG_H_INT_ESB;\n \tif (flags & XIVE_SRC_STORE_EOI)\n \t\tdata->flags |= XIVE_IRQ_FLAG_STORE_EOI;\n \tif (flags & XIVE_SRC_LSI)\n@@ -487,6 +528,7 @@ static const struct xive_ops xive_spapr_ops = {\n \t.setup_cpu\t\t= xive_spapr_setup_cpu,\n \t.teardown_cpu\t\t= xive_spapr_teardown_cpu,\n \t.sync_source\t\t= xive_spapr_sync_source,\n+\t.esb_rw\t\t\t= xive_spapr_esb_rw,\n #ifdef CONFIG_SMP\n \t.get_ipi\t\t= xive_spapr_get_ipi,\n \t.put_ipi\t\t= xive_spapr_put_ipi,\ndiff --git a/arch/powerpc/sysdev/xive/xive-internal.h b/arch/powerpc/sysdev/xive/xive-internal.h\nindex dd1e2022cce4..f34abed0c05f 100644\n--- a/arch/powerpc/sysdev/xive/xive-internal.h\n+++ b/arch/powerpc/sysdev/xive/xive-internal.h\n@@ -47,6 +47,7 @@ struct xive_ops {\n \tvoid\t(*update_pending)(struct xive_cpu *xc);\n \tvoid\t(*eoi)(u32 hw_irq);\n \tvoid\t(*sync_source)(u32 hw_irq);\n+\tu64\t(*esb_rw)(u32 hw_irq, u32 offset, u64 data, bool write);\n #ifdef CONFIG_SMP\n \tint\t(*get_ipi)(unsigned int cpu, struct xive_cpu *xc);\n \tvoid\t(*put_ipi)(unsigned int cpu, struct xive_cpu *xc);\n","prefixes":["v3","6/8"]}