{"id":807659,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807659/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170830142454.10971-3-jglauber@cavium.com>","date":"2017-08-30T14:24:53","name":"[v3,2/3] PCI: Avoid bus reset for Cavium cn8xxx root ports","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"82123b16b8e2bd0f304bf9826c08fcd4da239bfe","submitter":{"id":68350,"url":"http://patchwork.ozlabs.org/api/1.0/people/68350/?format=json","name":"Jan Glauber","email":"jglauber@cavium.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170830142454.10971-3-jglauber@cavium.com/mbox/","series":[{"id":624,"url":"http://patchwork.ozlabs.org/api/1.0/series/624/?format=json","date":"2017-08-30T14:24:51","name":"Workaround for bus/slot reset on Cavium cn8xxx root ports","version":3,"mbox":"http://patchwork.ozlabs.org/series/624/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807659/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj79d5Tbgz9s7f\n\tfor ;\n\tThu, 31 Aug 2017 00:26:45 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751525AbdH3O01 (ORCPT );\n\tWed, 30 Aug 2017 10:26:27 -0400","from mail-wm0-f66.google.com ([74.125.82.66]:34899 \"EHLO\n\tmail-wm0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751686AbdH3OZL (ORCPT\n\t); Wed, 30 Aug 2017 10:25:11 -0400","by mail-wm0-f66.google.com with SMTP id e204so1978615wma.2;\n\tWed, 30 Aug 2017 07:25:11 -0700 (PDT)","from hc.fritz.box\n\t(HSI-KBW-46-223-66-184.hsi.kabel-badenwuerttemberg.de.\n\t[46.223.66.184]) by smtp.gmail.com with ESMTPSA id\n\tp105sm97012wrc.64.2017.08.30.07.25.09\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 30 Aug 2017 07:25:10 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=Gpp9j+xHs+YKdmKAmr9f20Tm/49tQR4QPKIbT2gm1gE=;\n\tb=EOT8JT8yG6ytHnasUPN/E2v26keqeL9IT6XQ4iLr67mQb698mE5llpultd14ZJ31CE\n\txp6ibgav6RkzzoTe/Mq5uwxTD4/f7nautk/je7E0HL+DA7eNjL5bC8mvbiBqENuo33xC\n\tsAZBxasG8nxdslpQc4qvWsF1tRKbyNpdYhzzPY4voZNYJAGiuPzu/f4VSART2KFXE/l5\n\tHqq/TI22lanPg4tvophbzOB/6CmJr0ec5BbH5+oITooB3urWnZMv589OJkVM/UTcJyeG\n\t3iOTy+dGb4+df1Qtcm1IR4hLeUeiyEFuNPI10gQ9x4pzxSIYDPQyl8iQiWsSynZgjzPx\n\tXv+Q==","X-Gm-Message-State":"AHYfb5ibNOAMGfEefRloR88tT+mYME4BD1oMYUnQR6NojzrQEupkQjnu\n\t/P3qQVRNh1rW0Awv","X-Received":"by 10.28.159.141 with SMTP id i135mr1397498wme.153.1504103110511;\n\tWed, 30 Aug 2017 07:25:10 -0700 (PDT)","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, Alex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,\n\tJan Glauber ","Subject":"[PATCH v3 2/3] PCI: Avoid bus reset for Cavium cn8xxx root ports","Date":"Wed, 30 Aug 2017 16:24:53 +0200","Message-Id":"<20170830142454.10971-3-jglauber@cavium.com>","X-Mailer":"git-send-email 2.9.0.rc0.21.g7777322","In-Reply-To":"<20170830142454.10971-1-jglauber@cavium.com>","References":"<20170830142454.10971-1-jglauber@cavium.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: David Daney \n\nRoot ports of cn8xxx do not function after bus reset when used with\nsome e1000e and LSI HBA devices. Add a quirk to prevent bus reset on\nthese root ports.\n\nSigned-off-by: David Daney \n[jglauber@cavium.com: fixed typo and whitespaces]\nSigned-off-by: Jan Glauber \n---\n drivers/pci/quirks.c | 8 ++++++++\n 1 file changed, 8 insertions(+)","diff":"diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 6967c6b..85191b8 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -3364,6 +3364,14 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);\n DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);\n \n+/*\n+ * Root port on some Cavium CN8xxx chips do not successfully complete\n+ * a bus reset when used with certain types of child devices. Config\n+ * space access to the child may quit responding. Flag the root port\n+ * as not supporting bus reset.\n+ */\n+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);\n+\n static void quirk_no_pm_reset(struct pci_dev *dev)\n {\n \t/*\n","prefixes":["v3","2/3"]}