{"id":807657,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807657/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170830142454.10971-4-jglauber@cavium.com>","date":"2017-08-30T14:24:54","name":"[v3,3/3] PCI: Avoid slot reset for Cavium cn8xxx root ports","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"6e7aaa188485bcdc5d2f78eec0ee7042b22ae249","submitter":{"id":68350,"url":"http://patchwork.ozlabs.org/api/1.0/people/68350/?format=json","name":"Jan Glauber","email":"jglauber@cavium.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170830142454.10971-4-jglauber@cavium.com/mbox/","series":[{"id":624,"url":"http://patchwork.ozlabs.org/api/1.0/series/624/?format=json","date":"2017-08-30T14:24:51","name":"Workaround for bus/slot reset on Cavium cn8xxx root ports","version":3,"mbox":"http://patchwork.ozlabs.org/series/624/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807657/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj78N6nqKz9s7f\n\tfor ;\n\tThu, 31 Aug 2017 00:25:40 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751805AbdH3OZj (ORCPT );\n\tWed, 30 Aug 2017 10:25:39 -0400","from mail-wm0-f68.google.com ([74.125.82.68]:34125 \"EHLO\n\tmail-wm0-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751706AbdH3OZM (ORCPT\n\t); Wed, 30 Aug 2017 10:25:12 -0400","by mail-wm0-f68.google.com with SMTP id l19so1979867wmi.1;\n\tWed, 30 Aug 2017 07:25:12 -0700 (PDT)","from hc.fritz.box\n\t(HSI-KBW-46-223-66-184.hsi.kabel-badenwuerttemberg.de.\n\t[46.223.66.184]) by smtp.gmail.com with ESMTPSA id\n\tp105sm97012wrc.64.2017.08.30.07.25.10\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 30 Aug 2017 07:25:11 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=6g0lkFSiY9+qwTZSmr4T+XOmcNxS9eDdmyr5PhhfFK0=;\n\tb=E5WNH+qjaFjqSlPz1Wg4t2wusFxiYHkuBCHDnuV2PBfkx30yFxnP6Ij0ibjq84RjkW\n\tCabwjmTVBrVZGxtkBOcZOowHMxAnybG0TvTPEJb1psw+bQJT5TtNbIUp2Ou+/EvBfZIx\n\tcayq+s/U3LW96n+WwvboI7op+T+zxGU2ucXX0wECM8OTrADfJLBTz7GfOFaPsGoy7bhU\n\tF+aCCF0FJiaHUTCP7cJHfkHjbPxsrpyf7afzDTRrZrxdUKMAtAGAdLrkUJvwqRa5OLEB\n\tagLU61OrKJVNmIBgFBwtSH72ZsvMMtpxMfs6qwJk4q0lgRCm8IHvP0/QQoIjxE+8ryNv\n\tSLng==","X-Gm-Message-State":"AHYfb5gyYDrycLOQ21eUDj+tfsjXtAJRREWnnttcn3Q7ytmrQYngSJm5\n\toWxke25Nmxky2EII","X-Received":"by 10.28.92.203 with SMTP id q194mr1636271wmb.165.1504103111476; \n\tWed, 30 Aug 2017 07:25:11 -0700 (PDT)","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, Alex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,\n\tJan Glauber ","Subject":"[PATCH v3 3/3] PCI: Avoid slot reset for Cavium cn8xxx root ports","Date":"Wed, 30 Aug 2017 16:24:54 +0200","Message-Id":"<20170830142454.10971-4-jglauber@cavium.com>","X-Mailer":"git-send-email 2.9.0.rc0.21.g7777322","In-Reply-To":"<20170830142454.10971-1-jglauber@cavium.com>","References":"<20170830142454.10971-1-jglauber@cavium.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"Root ports of cn8xxx do not function after a slot reset when used with\nsome e1000e and LSI HBA devices. Add a quirk to prevent slot reset on\nthese root ports.\n\nSigned-off-by: Jan Glauber \n---\n drivers/pci/quirks.c | 16 ++++++++++++++++\n 1 file changed, 16 insertions(+)","diff":"diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex 85191b8..6679971 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -845,6 +845,22 @@ static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);\n #endif\n \n+/*\n+ * Root port on some Cavium CN8xxx chips do not successfully complete\n+ * a bus reset when used with certain types of child devices. Config\n+ * space access to the child may quit responding. Flag all devices under\n+ * the secondary bus as non-resettable.\n+ */\n+static void quirk_CN8xxx_secondary_bus(struct pci_dev *dev)\n+{\n+\tstruct pci_dev *pdev;\n+\n+\tdev_warn(&dev->dev, \"Cavium CN8xxx quirk detected; reset for devices on secondary bus disabled\\n\");\n+\tlist_for_each_entry(pdev, &dev->subordinate->devices, bus_list)\n+\t\tpdev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;\n+}\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_CN8xxx_secondary_bus);\n+\n /*\n * Some settings of MMRBC can lead to data corruption so block changes.\n * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide\n","prefixes":["v3","3/3"]}