{"id":807656,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807656/?format=json","project":{"id":28,"url":"http://patchwork.ozlabs.org/api/1.0/projects/28/?format=json","name":"Linux PCI development","link_name":"linux-pci","list_id":"linux-pci.vger.kernel.org","list_email":"linux-pci@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null},"msgid":"<20170830142454.10971-2-jglauber@cavium.com>","date":"2017-08-30T14:24:52","name":"[v3,1/3] PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"65c8c059234e4a22d2dacaeab8f51002b7d9cb53","submitter":{"id":68350,"url":"http://patchwork.ozlabs.org/api/1.0/people/68350/?format=json","name":"Jan Glauber","email":"jglauber@cavium.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-pci/patch/20170830142454.10971-2-jglauber@cavium.com/mbox/","series":[{"id":624,"url":"http://patchwork.ozlabs.org/api/1.0/series/624/?format=json","date":"2017-08-30T14:24:51","name":"Workaround for bus/slot reset on Cavium cn8xxx root ports","version":3,"mbox":"http://patchwork.ozlabs.org/series/624/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807656/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj77v2503z9s8J\n\tfor ;\n\tThu, 31 Aug 2017 00:25:15 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751728AbdH3OZN (ORCPT );\n\tWed, 30 Aug 2017 10:25:13 -0400","from mail-wm0-f66.google.com ([74.125.82.66]:37842 \"EHLO\n\tmail-wm0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751683AbdH3OZK (ORCPT\n\t); Wed, 30 Aug 2017 10:25:10 -0400","by mail-wm0-f66.google.com with SMTP id x189so1968587wmg.4;\n\tWed, 30 Aug 2017 07:25:10 -0700 (PDT)","from hc.fritz.box\n\t(HSI-KBW-46-223-66-184.hsi.kabel-badenwuerttemberg.de.\n\t[46.223.66.184]) by smtp.gmail.com with ESMTPSA id\n\tp105sm97012wrc.64.2017.08.30.07.25.08\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tWed, 30 Aug 2017 07:25:09 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=qaphwBHb+zU3ev3NVN7TOSSreMynoGbonAUKptoAR3s=;\n\tb=Q7Be0V5YFJWooHnBIxRvMBFzu2pXzXwy4k2+z1z2SNpOwLQAPBlXRvlyn9EIaaSD7W\n\th/KU52f3HyMY8mxvBG3D9Tp0wJSkJFP4c/nK47Ajhkx7TMwAY7/yaSvZnu+fqxPoyztR\n\tagOPDHlJLp5Wpi3FxnI6ijv+rnDTImr67yObbLHwW3B95g9uL12iIO5l+t6bLqF/3RiA\n\tZF1MNZmNU0MQvY6kgahE/eLOtRsEWKAVV5C/s923N5ZB2ZywEEj3k3gUPLaIW8CiLlA/\n\tpp2wy5J9zXmfts6hNbRP3W8J+dUNISUQbyfTHuXBYP6/PTbEKibyrYYrqO0jdrtpV1km\n\tNjAg==","X-Gm-Message-State":"AHYfb5i+Tr6wjyyZma0rfYdr7Fi2ioijGX2Zcr334IwAw2RtQYC7n/H/\n\t5U1vE2p7KpuOAw==","X-Received":"by 10.28.157.19 with SMTP id g19mr1312673wme.42.1504103109598;\n\tWed, 30 Aug 2017 07:25:09 -0700 (PDT)","From":"Jan Glauber ","To":"Bjorn Helgaas ","Cc":"linux-pci@vger.kernel.org, Alex Williamson ,\n\tlinux-kernel@vger.kernel.org, david.daney@cavium.com,\n\tJon Masters , Robert Richter ,\n\tlinux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org,\n\tJan Glauber ","Subject":"[PATCH v3 1/3] PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on\n\tbus device","Date":"Wed, 30 Aug 2017 16:24:52 +0200","Message-Id":"<20170830142454.10971-2-jglauber@cavium.com>","X-Mailer":"git-send-email 2.9.0.rc0.21.g7777322","In-Reply-To":"<20170830142454.10971-1-jglauber@cavium.com>","References":"<20170830142454.10971-1-jglauber@cavium.com>","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"},"content":"From: David Daney \n\nWhen checking to see if a PCI bus can safely be reset, we check to see\nif any of the children have their PCI_DEV_FLAGS_NO_BUS_RESET flag set.\nAs these devices are known not to behave well after a bus reset.\n\nSome PCIe root port bridges also do not behave well after a bus reset,\nsometimes causing the devices behind the bridge to become unusable.\n\nAdd a check for the PCI_DEV_FLAGS_NO_BUS_RESET flag being set in the\nbridge device to allow these bridges to be flagged, and prevent their\nbuses from being reset.\n\nA follow on patch will add a quirk for this type of bridge.\n\nSigned-off-by: David Daney \n[jglauber@cavium.com: fixed typo]\nSigned-off-by: Jan Glauber \n---\n drivers/pci/pci.c | 4 ++++\n 1 file changed, 4 insertions(+)","diff":"diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex af0cc34..d9abbc9 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -4290,6 +4290,10 @@ static bool pci_bus_resetable(struct pci_bus *bus)\n {\n \tstruct pci_dev *dev;\n \n+\n+\tif (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))\n+\t\treturn false;\n+\n \tlist_for_each_entry(dev, &bus->devices, bus_list) {\n \t\tif (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||\n \t\t (dev->subordinate && !pci_bus_resetable(dev->subordinate)))\n","prefixes":["v3","1/3"]}