{"id":807480,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807480/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20170830082702.3011-9-Sergio.G.DelReal@gmail.com>","date":"2017-08-30T08:26:57","name":"[v2,08/13] hvf: implement hvf_get_supported_cpuid","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2ded40ea4c564b4f81b954bf9cf9d064c3b32b27","submitter":{"id":70675,"url":"http://patchwork.ozlabs.org/api/1.0/people/70675/?format=json","name":"Sergio Andres Gomez Del Real","email":"sergio.g.delreal@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170830082702.3011-9-Sergio.G.DelReal@gmail.com/mbox/","series":[{"id":548,"url":"http://patchwork.ozlabs.org/api/1.0/series/548/?format=json","date":"2017-08-30T08:26:49","name":"add support for Hypervisor.framework in QEMU","version":2,"mbox":"http://patchwork.ozlabs.org/series/548/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807480/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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/* core2duo */\n@@ -277,3 +299,119 @@ void get_cpuid_func(struct CPUState *cpu, int func, int cnt, uint32_t *eax,\n break;\n }\n }\n+\n+uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx,\n+ int reg)\n+{\n+ uint64_t cap;\n+ uint32_t eax, ebx, ecx, edx;\n+\n+ host_cpuid(func, idx, &eax, &ebx, &ecx, &edx);\n+\n+ switch (func) {\n+ case 0:\n+ eax = eax < (uint32_t)0xd ? eax : (uint32_t)0xd;\n+ break;\n+ case 1:\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX |\n+ CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS;\n+ ecx &= CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |\n+ CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID |\n+ CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_MOVBE |\n+ CPUID_EXT_POPCNT | CPUID_EXT_AES | CPUID_EXT_XSAVE |\n+ CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND;\n+ break;\n+ case 6:\n+ eax = 4;\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ break;\n+ case 7:\n+ if (idx == 0) {\n+ ebx &= CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |\n+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 |\n+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |\n+ CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_RTM |\n+ CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |\n+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_AVX512IFMA |\n+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512PF |\n+ CPUID_7_0_EBX_AVX512ER | CPUID_7_0_EBX_AVX512CD |\n+ CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB |\n+ CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI |\n+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL |\n+ CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_MPX;\n+\n+ if (!vmx_mpx_supported()) {\n+ ebx &= ~CPUID_7_0_EBX_MPX;\n+ }\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);\n+ if (!(cap & CPU_BASED2_INVPCID)) {\n+ ebx &= ~CPUID_7_0_EBX_INVPCID;\n+ }\n+\n+ ecx &= CPUID_7_0_ECX_AVX512BMI | CPUID_7_0_ECX_AVX512_VPOPCNTDQ;\n+ edx &= CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS;\n+ } else {\n+ ebx = 0;\n+ ecx = 0;\n+ edx = 0;\n+ }\n+ eax = 0;\n+ break;\n+ case 0xD:\n+ if (idx == 0) {\n+ uint64_t host_xcr0 = xgetbv(0);\n+ uint64_t supp_xcr0 = host_xcr0 & (XSTATE_FP_MASK | XSTATE_SSE_MASK |\n+ XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK |\n+ XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |\n+ XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK);\n+ eax &= supp_xcr0;\n+ if (!vmx_mpx_supported()) {\n+ eax &= ~(XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK);\n+ }\n+ } else if (idx == 1) {\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap);\n+ eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1;\n+ if (!(cap & CPU_BASED2_XSAVES_XRSTORS)) {\n+ eax &= ~CPUID_XSAVE_XSAVES;\n+ }\n+ }\n+ break;\n+ case 0x80000001:\n+ /* LM only if HVF in 64-bit mode */\n+ edx &= CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |\n+ CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |\n+ CPUID_EXT2_SYSCALL | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |\n+ CPUID_PAT | CPUID_PSE36 | CPUID_EXT2_MMXEXT | CPUID_MMX |\n+ CPUID_FXSR | CPUID_EXT2_FXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_3DNOWEXT |\n+ CPUID_EXT2_3DNOW | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX;\n+ hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &cap);\n+ if (!(cap & CPU_BASED_TSC_OFFSET)) {\n+ edx &= ~CPUID_EXT2_RDTSCP;\n+ }\n+ ecx &= CPUID_EXT3_LAHF_LM | CPUID_EXT3_CMP_LEG | CPUID_EXT3_CR8LEG |\n+ CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE |\n+ CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_OSVW | CPUID_EXT3_XOP |\n+ CPUID_EXT3_FMA4 | CPUID_EXT3_TBM;\n+ break;\n+ default:\n+ return 0;\n+ }\n+\n+ switch (reg) {\n+ case R_EAX:\n+ return eax;\n+ case R_EBX:\n+ return ebx;\n+ case R_ECX:\n+ return ecx;\n+ case R_EDX:\n+ return edx;\n+ default:\n+ return 0;\n+ }\n+}\n","prefixes":["v2","08/13"]}