{"id":807447,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807447/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<20170830063409.GE27329@fergus.ozlabs.ibm.com>","date":"2017-08-30T06:34:09","name":"[v3,18/17] powerpc: Emulate load/store floating point as integer word instructions","commit_ref":"d2b65ac6526a82965212b632d42687251e122a36","pull_url":null,"state":"accepted","archived":false,"hash":"9aa6cdba6137d79426bfec65848d00a9ef5a9cec","submitter":{"id":67079,"url":"http://patchwork.ozlabs.org/api/1.0/people/67079/?format=json","name":"Paul Mackerras","email":"paulus@ozlabs.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170830063409.GE27329@fergus.ozlabs.ibm.com/mbox/","series":[{"id":522,"url":"http://patchwork.ozlabs.org/api/1.0/series/522/?format=json","date":"2017-08-30T04:12:25","name":"powerpc: Do alignment fixups using analyse_instr etc.","version":3,"mbox":"http://patchwork.ozlabs.org/series/522/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807447/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhwkP3Sg0z9sN7\n\tfor ;\n\tWed, 30 Aug 2017 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dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"R0l1v8O0\"; \n\tdkim-atps=neutral"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504074860; bh=rvAy7dJocg+JIPpopa73gX+MLkUi9nriy9iZ9FJgM3I=;\n\th=Date:From:To:Subject:References:In-Reply-To:From;\n\tb=R0l1v8O0gj2UWLGZCzOIKQRao3UAx9wkKaXt/OebHGdFrsaOW/vuZoP+rXJntDwpj\n\tMJuW7f3KVPm97zvfOCk5M4AtZwFn4s7lmpasP7f8agBAdMbJjpR9wB20s2dKue4kT/\n\teE2i6aQAcluJOeeSdVb7TGnPSMgOG6HrulNK68qGKYBHlnDuHqaxhmMme+cu8yPXo2\n\tDKkt4tH4Su4bmqRkEc445Xwuka+d0Vgeeb/1Yv9eMmXMbb7kpraTuYpRZp3ufgUr12\n\tqGZshmFLNuahaoRTWUyWkJAoCv3GQxGJlubuZk2Dp/XTBg64txk3bZQ7Y+DbwcKsFe\n\tMtOCu/o2S+pTg==","Date":"Wed, 30 Aug 2017 16:34:09 +1000","From":"Paul Mackerras ","To":"linuxppc-dev@ozlabs.org","Subject":"[PATCH v3 18/17] powerpc: Emulate load/store floating point as\n\tinteger word instructions","Message-ID":"<20170830063409.GE27329@fergus.ozlabs.ibm.com>","References":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","User-Agent":"Mutt/1.5.24 (2015-08-30)","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"This adds emulation for the lfiwax, lfiwzx and stfiwx instructions.\nThis necessitated adding a new flag to indicate whether a floating\npoint or an integer conversion was needed for LOAD_FP and STORE_FP,\nso this moves the size field in op->type up 4 bits.\n\nSigned-off-by: Paul Mackerras \n---\n arch/powerpc/include/asm/sstep.h | 5 ++--\n arch/powerpc/lib/sstep.c | 60 ++++++++++++++++++++++++++++++----------\n 2 files changed, 48 insertions(+), 17 deletions(-)","diff":"diff --git a/arch/powerpc/include/asm/sstep.h b/arch/powerpc/include/asm/sstep.h\nindex 309d1c5..ab9d849 100644\n--- a/arch/powerpc/include/asm/sstep.h\n+++ b/arch/powerpc/include/asm/sstep.h\n@@ -68,6 +68,7 @@ enum instruction_type {\n #define SIGNEXT\t\t0x20\n #define UPDATE\t\t0x40\t/* matches bit in opcode 31 instructions */\n #define BYTEREV\t\t0x80\n+#define FPCONV\t\t0x100\n \n /* Barrier type field, ORed in with type */\n #define BARRIER_MASK\t0xe0\n@@ -93,8 +94,8 @@ enum instruction_type {\n #define VSX_CHECK_VEC\t8\t/* check MSR_VEC not MSR_VSX for reg >= 32 */\n \n /* Size field in type word */\n-#define SIZE(n)\t\t((n) << 8)\n-#define GETSIZE(w)\t((w) >> 8)\n+#define SIZE(n)\t\t((n) << 12)\n+#define GETSIZE(w)\t((w) >> 12)\n \n #define MKOP(t, f, s)\t((t) | (f) | SIZE(s))\n \ndiff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 24031ca..2f6897c 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -457,19 +457,23 @@ NOKPROBE_SYMBOL(write_mem);\n * These access either the real FP register or the image in the\n * thread_struct, depending on regs->msr & MSR_FP.\n */\n-static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs,\n-\t\t bool cross_endian)\n+static int do_fp_load(struct instruction_op *op, unsigned long ea,\n+\t\t struct pt_regs *regs, bool cross_endian)\n {\n-\tint err;\n+\tint err, rn, nb;\n \tunion {\n+\t\tint i;\n+\t\tunsigned int u;\n \t\tfloat f;\n \t\tdouble d[2];\n \t\tunsigned long l[2];\n \t\tu8 b[2 * sizeof(double)];\n \t} u;\n \n+\tnb = GETSIZE(op->type);\n \tif (!address_ok(regs, ea, nb))\n \t\treturn -EFAULT;\n+\trn = op->reg;\n \terr = copy_mem_in(u.b, ea, nb, regs);\n \tif (err)\n \t\treturn err;\n@@ -479,8 +483,14 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs,\n \t\t\tdo_byte_reverse(&u.b[8], 8);\n \t}\n \tpreempt_disable();\n-\tif (nb == 4)\n-\t\tconv_sp_to_dp(&u.f, &u.d[0]);\n+\tif (nb == 4) {\n+\t\tif (op->type & FPCONV)\n+\t\t\tconv_sp_to_dp(&u.f, &u.d[0]);\n+\t\telse if (op->type & SIGNEXT)\n+\t\t\tu.l[0] = u.i;\n+\t\telse\n+\t\t\tu.l[0] = u.u;\n+\t}\n \tif (regs->msr & MSR_FP)\n \t\tput_fpr(rn, &u.d[0]);\n \telse\n@@ -498,25 +508,33 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs,\n }\n NOKPROBE_SYMBOL(do_fp_load);\n \n-static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs,\n-\t\t bool cross_endian)\n+static int do_fp_store(struct instruction_op *op, unsigned long ea,\n+\t\t struct pt_regs *regs, bool cross_endian)\n {\n+\tint rn, nb;\n \tunion {\n+\t\tunsigned int u;\n \t\tfloat f;\n \t\tdouble d[2];\n \t\tunsigned long l[2];\n \t\tu8 b[2 * sizeof(double)];\n \t} u;\n \n+\tnb = GETSIZE(op->type);\n \tif (!address_ok(regs, ea, nb))\n \t\treturn -EFAULT;\n+\trn = op->reg;\n \tpreempt_disable();\n \tif (regs->msr & MSR_FP)\n \t\tget_fpr(rn, &u.d[0]);\n \telse\n \t\tu.l[0] = current->thread.TS_FPR(rn);\n-\tif (nb == 4)\n-\t\tconv_dp_to_sp(&u.d[0], &u.f);\n+\tif (nb == 4) {\n+\t\tif (op->type & FPCONV)\n+\t\t\tconv_dp_to_sp(&u.d[0], &u.f);\n+\t\telse\n+\t\t\tu.u = u.l[0];\n+\t}\n \tif (nb == 16) {\n \t\trn |= 1;\n \t\tif (regs->msr & MSR_FP)\n@@ -2049,7 +2067,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #ifdef CONFIG_PPC_FPU\n \t\tcase 535:\t/* lfsx */\n \t\tcase 567:\t/* lfsux */\n-\t\t\top->type = MKOP(LOAD_FP, u, 4);\n+\t\t\top->type = MKOP(LOAD_FP, u | FPCONV, 4);\n \t\t\tbreak;\n \n \t\tcase 599:\t/* lfdx */\n@@ -2059,7 +2077,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \n \t\tcase 663:\t/* stfsx */\n \t\tcase 695:\t/* stfsux */\n-\t\t\top->type = MKOP(STORE_FP, u, 4);\n+\t\t\top->type = MKOP(STORE_FP, u | FPCONV, 4);\n \t\t\tbreak;\n \n \t\tcase 727:\t/* stfdx */\n@@ -2072,9 +2090,21 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\top->type = MKOP(LOAD_FP, 0, 16);\n \t\t\tbreak;\n \n+\t\tcase 855:\t/* lfiwax */\n+\t\t\top->type = MKOP(LOAD_FP, SIGNEXT, 4);\n+\t\t\tbreak;\n+\n+\t\tcase 887:\t/* lfiwzx */\n+\t\t\top->type = MKOP(LOAD_FP, 0, 4);\n+\t\t\tbreak;\n+\n \t\tcase 919:\t/* stfdpx */\n \t\t\top->type = MKOP(STORE_FP, 0, 16);\n \t\t\tbreak;\n+\n+\t\tcase 983:\t/* stfiwx */\n+\t\t\top->type = MKOP(STORE_FP, 0, 4);\n+\t\t\tbreak;\n #endif /* __powerpc64 */\n #endif /* CONFIG_PPC_FPU */\n \n@@ -2352,7 +2382,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #ifdef CONFIG_PPC_FPU\n \tcase 48:\t/* lfs */\n \tcase 49:\t/* lfsu */\n-\t\top->type = MKOP(LOAD_FP, u, 4);\n+\t\top->type = MKOP(LOAD_FP, u | FPCONV, 4);\n \t\top->ea = dform_ea(instr, regs);\n \t\tbreak;\n \n@@ -2364,7 +2394,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \n \tcase 52:\t/* stfs */\n \tcase 53:\t/* stfsu */\n-\t\top->type = MKOP(STORE_FP, u, 4);\n+\t\top->type = MKOP(STORE_FP, u | FPCONV, 4);\n \t\top->ea = dform_ea(instr, regs);\n \t\tbreak;\n \n@@ -2792,7 +2822,7 @@ int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)\n \t\t */\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))\n \t\t\treturn 0;\n-\t\terr = do_fp_load(op->reg, ea, size, regs, cross_endian);\n+\t\terr = do_fp_load(op, ea, regs, cross_endian);\n \t\tbreak;\n #endif\n #ifdef CONFIG_ALTIVEC\n@@ -2862,7 +2892,7 @@ int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)\n \tcase STORE_FP:\n \t\tif (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))\n \t\t\treturn 0;\n-\t\terr = do_fp_store(op->reg, ea, size, regs, cross_endian);\n+\t\terr = do_fp_store(op, ea, regs, cross_endian);\n \t\tbreak;\n #endif\n #ifdef CONFIG_ALTIVEC\n","prefixes":["v3","18/17"]}