{"id":807404,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807404/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<1504066360-30128-13-git-send-email-paulus@ozlabs.org>","date":"2017-08-30T04:12:35","name":"[v3,12/17] powerpc: Emulate load/store floating double pair instructions","commit_ref":"1f41fb790460acf432f826f4aeeff6f7da891ff7","pull_url":null,"state":"accepted","archived":false,"hash":"2bf44f7d20c4147cc9803744e605f07b5f229454","submitter":{"id":67079,"url":"http://patchwork.ozlabs.org/api/1.0/people/67079/?format=json","name":"Paul Mackerras","email":"paulus@ozlabs.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-13-git-send-email-paulus@ozlabs.org/mbox/","series":[{"id":522,"url":"http://patchwork.ozlabs.org/api/1.0/series/522/?format=json","date":"2017-08-30T04:12:25","name":"powerpc: Do alignment fixups using analyse_instr etc.","version":3,"mbox":"http://patchwork.ozlabs.org/series/522/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807404/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xht580wtdz9s9Y\n\tfor ;\n\tWed, 30 Aug 2017 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header.b=\"a3T57Wl6\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"a3T57Wl6\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"a3T57Wl6\"; \n\tdkim-atps=neutral"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504066372; bh=lEusDxlc3WxvcsVGzzFCIBJkyPYQRb/c42UpF8qwVxo=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=a3T57Wl6y6LeMk4kwB3KetglhjMC5PTsF2C4XwNuYBMYAaaOQ3NQutfp0xpATIb5a\n\tQ8fLB+c3QAnyGi2d1FONfSWjjD7ZgEvEnd0ZLaMQLYZj4x5UhLN69J++n1Wba/se64\n\tGLzSCLnmDr0KOpiViHhEFGzlcMIVuBJnoQGcDABNVc2Ao0ZRkWmEqMpPSbT4+UdEX8\n\tYAn+j7VDw8dfB8V4UU7yiOQukuPwvte919n8GZP5kURPvTYjKb6PeK6egYbY46Pr7e\n\tbKDThXRz2DM/itpVextgQKbwmSig6hLLmjYX3koo+LPuE22rD25ynAZX/ddCNXBJFd\n\tJQZmM5LckMz3A==","From":"Paul Mackerras ","To":"linuxppc-dev@ozlabs.org","Subject":"[PATCH v3 12/17] powerpc: Emulate load/store floating double pair\n\tinstructions","Date":"Wed, 30 Aug 2017 14:12:35 +1000","Message-Id":"<1504066360-30128-13-git-send-email-paulus@ozlabs.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","References":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"This adds lfdp[x] and stfdp[x] to the set of instructions that\nanalyse_instr() and emulate_step() understand.\n\nSigned-off-by: Paul Mackerras \n---\n arch/powerpc/lib/sstep.c | 68 ++++++++++++++++++++++++++++++++++++------------\n 1 file changed, 52 insertions(+), 16 deletions(-)","diff":"diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 167d40d..817cdc9 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -415,9 +415,9 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n \tint err;\n \tunion {\n \t\tfloat f;\n-\t\tdouble d;\n-\t\tunsigned long l;\n-\t\tu8 b[sizeof(double)];\n+\t\tdouble d[2];\n+\t\tunsigned long l[2];\n+\t\tu8 b[2 * sizeof(double)];\n \t} u;\n \n \tif (!address_ok(regs, ea, nb))\n@@ -427,11 +427,19 @@ static int do_fp_load(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n \t\treturn err;\n \tpreempt_disable();\n \tif (nb == 4)\n-\t\tconv_sp_to_dp(&u.f, &u.d);\n+\t\tconv_sp_to_dp(&u.f, &u.d[0]);\n \tif (regs->msr & MSR_FP)\n-\t\tput_fpr(rn, &u.d);\n+\t\tput_fpr(rn, &u.d[0]);\n \telse\n-\t\tcurrent->thread.TS_FPR(rn) = u.l;\n+\t\tcurrent->thread.TS_FPR(rn) = u.l[0];\n+\tif (nb == 16) {\n+\t\t/* lfdp */\n+\t\trn |= 1;\n+\t\tif (regs->msr & MSR_FP)\n+\t\t\tput_fpr(rn, &u.d[1]);\n+\t\telse\n+\t\t\tcurrent->thread.TS_FPR(rn) = u.l[1];\n+\t}\n \tpreempt_enable();\n \treturn 0;\n }\n@@ -441,20 +449,27 @@ static int do_fp_store(int rn, unsigned long ea, int nb, struct pt_regs *regs)\n {\n \tunion {\n \t\tfloat f;\n-\t\tdouble d;\n-\t\tunsigned long l;\n-\t\tu8 b[sizeof(double)];\n+\t\tdouble d[2];\n+\t\tunsigned long l[2];\n+\t\tu8 b[2 * sizeof(double)];\n \t} u;\n \n \tif (!address_ok(regs, ea, nb))\n \t\treturn -EFAULT;\n \tpreempt_disable();\n \tif (regs->msr & MSR_FP)\n-\t\tget_fpr(rn, &u.d);\n+\t\tget_fpr(rn, &u.d[0]);\n \telse\n-\t\tu.l = current->thread.TS_FPR(rn);\n+\t\tu.l[0] = current->thread.TS_FPR(rn);\n \tif (nb == 4)\n-\t\tconv_dp_to_sp(&u.d, &u.f);\n+\t\tconv_dp_to_sp(&u.d[0], &u.f);\n+\tif (nb == 16) {\n+\t\trn |= 1;\n+\t\tif (regs->msr & MSR_FP)\n+\t\t\tget_fpr(rn, &u.d[1]);\n+\t\telse\n+\t\t\tu.l[1] = current->thread.TS_FPR(rn);\n+\t}\n \tpreempt_enable();\n \treturn copy_mem_out(u.b, ea, nb);\n }\n@@ -1938,7 +1953,17 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\tcase 759:\t/* stfdux */\n \t\t\top->type = MKOP(STORE_FP, u, 8);\n \t\t\tbreak;\n-#endif\n+\n+#ifdef __powerpc64__\n+\t\tcase 791:\t/* lfdpx */\n+\t\t\top->type = MKOP(LOAD_FP, 0, 16);\n+\t\t\tbreak;\n+\n+\t\tcase 919:\t/* stfdpx */\n+\t\t\top->type = MKOP(STORE_FP, 0, 16);\n+\t\t\tbreak;\n+#endif /* __powerpc64 */\n+#endif /* CONFIG_PPC_FPU */\n \n #ifdef __powerpc64__\n \t\tcase 660:\t/* stdbrx */\n@@ -1956,7 +1981,7 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\top->val = byterev_4(regs->gpr[rd]);\n \t\t\tbreak;\n \n-\t\tcase 725:\n+\t\tcase 725:\t/* stswi */\n \t\t\tif (rb == 0)\n \t\t\t\trb = 32;\t/* # bytes to store */\n \t\t\top->type = MKOP(STORE_MULTI, 0, rb);\n@@ -2246,9 +2271,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #endif\n \n #ifdef CONFIG_VSX\n-\tcase 57:\t/* lxsd, lxssp */\n+\tcase 57:\t/* lfdp, lxsd, lxssp */\n \t\top->ea = dsform_ea(instr, regs);\n \t\tswitch (instr & 3) {\n+\t\tcase 0:\t\t/* lfdp */\n+\t\t\tif (rd & 1)\n+\t\t\t\tbreak;\t\t/* reg must be even */\n+\t\t\top->type = MKOP(LOAD_FP, 0, 16);\n+\t\t\tbreak;\n \t\tcase 2:\t\t/* lxsd */\n \t\t\top->reg = rd + 32;\n \t\t\top->type = MKOP(LOAD_VSX, 0, 8);\n@@ -2283,8 +2313,14 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #endif\n \n #ifdef CONFIG_VSX\n-\tcase 61:\t/* lxv, stxsd, stxssp, stxv */\n+\tcase 61:\t/* stfdp, lxv, stxsd, stxssp, stxv */\n \t\tswitch (instr & 7) {\n+\t\tcase 0:\t\t/* stfdp with LSB of DS field = 0 */\n+\t\tcase 4:\t\t/* stfdp with LSB of DS field = 1 */\n+\t\t\top->ea = dsform_ea(instr, regs);\n+\t\t\top->type = MKOP(STORE_FP, 0, 16);\n+\t\t\tbreak;\n+\n \t\tcase 1:\t\t/* lxv */\n \t\t\top->ea = dqform_ea(instr, regs);\n \t\t\tif (instr & 8)\n","prefixes":["v3","12/17"]}