{"id":807391,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807391/?format=json","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.0/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/"},"msgid":"<1504066360-30128-4-git-send-email-paulus@ozlabs.org>","date":"2017-08-30T04:12:26","name":"[v3,03/17] powerpc: Don't check MSR FP/VMX/VSX enable bits in analyse_instr()","commit_ref":"ee0a54d7978874fb2ba3b1e61e88ffffd31fcbc9","pull_url":null,"state":"accepted","archived":false,"hash":"9fd555e0d02b0a4a55eb8d19c82a11bbeeb8616a","submitter":{"id":67079,"url":"http://patchwork.ozlabs.org/api/1.0/people/67079/?format=json","name":"Paul Mackerras","email":"paulus@ozlabs.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504066360-30128-4-git-send-email-paulus@ozlabs.org/mbox/","series":[{"id":522,"url":"http://patchwork.ozlabs.org/api/1.0/series/522/?format=json","date":"2017-08-30T04:12:25","name":"powerpc: Do alignment fixups using analyse_instr etc.","version":3,"mbox":"http://patchwork.ozlabs.org/series/522/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807391/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhsdD6vcbz9sNc\n\tfor ;\n\tWed, 30 Aug 2017 14:16:16 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xhsdD5dypzDqMM\n\tfor ;\n\tWed, 30 Aug 2017 14:16:16 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xhsYG1cRkzDqGX\n\tfor ;\n\tWed, 30 Aug 2017 14:12:50 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xhsYG107yz9sR9; Wed, 30 Aug 2017 14:12:50 +1000 (AEST)","from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xhsYF6xrZz9sPt\n\tfor ; Wed, 30 Aug 2017 14:12:49 +1000 (AEST)"],"Authentication-Results":["ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"YqF2IAch\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"YqF2IAch\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"YqF2IAch\"; \n\tdkim-atps=neutral"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1504066370; bh=N+Z9y2ehwUFMPKEal9mO9LFgEVGcqRZTznXLqHfXzec=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=YqF2IAchA5pL7e0t8jgOqvPXcNcwz2fb/457MjnQ6/H8fTA2yOwkNknInMRECeatm\n\tYeYLg2gAmAHy8X7dJiz8xzvvufBaBnekBgZAzWnzBBUEUzMgKeMayRpnkVwbH9yUgt\n\tpBWasWI+pbz622kayw0l3/x6xSFJbPoqZ1wprtEk9MMd23ukTeEY4b0QNAR0nrOpKy\n\tJIYgaEHNuYsYNp47s8G04Dgr8pPaEG3tta2so8iAvjbxmpl2Lk0OMO6AmLiT27+/aO\n\tqxfE/jjiFoeIFXvwm2g4lJjhq/UoE1BQUccmqno5lfNI8n1xKqMnyOkY7OcGUaYkv1\n\tku8C1NeYWgpxg==","From":"Paul Mackerras ","To":"linuxppc-dev@ozlabs.org","Subject":"[PATCH v3 03/17] powerpc: Don't check MSR FP/VMX/VSX enable bits in\n\tanalyse_instr()","Date":"Wed, 30 Aug 2017 14:12:26 +1000","Message-Id":"<1504066360-30128-4-git-send-email-paulus@ozlabs.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","References":"<1504066360-30128-1-git-send-email-paulus@ozlabs.org>","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"This removes the checks for the FP/VMX/VSX enable bits in the MSR\nfrom analyse_instr() and adds them to emulate_step() instead.\n\nThe reason for this is that we may want to use analyse_instr() in\na situation where the FP/VMX/VSX register values are stored in the\ncurrent thread_struct and the FP/VMX/VSX enable bits in the MSR\nimage in the pt_regs are zero. Since analyse_instr() doesn't make\nany changes to register state, it is reasonable for it to indicate\nwhat the effect of an instruction would be even though the relevant\nenable bit is off.\n\nSigned-off-by: Paul Mackerras \n---\n arch/powerpc/lib/sstep.c | 54 +++++++++++-------------------------------------\n 1 file changed, 12 insertions(+), 42 deletions(-)","diff":"diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 8e581c6..13733b7 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -1505,15 +1505,11 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #ifdef CONFIG_ALTIVEC\n \t\tcase 103:\t/* lvx */\n \t\tcase 359:\t/* lvxl */\n-\t\t\tif (!(regs->msr & MSR_VEC))\n-\t\t\t\tgoto vecunavail;\n \t\t\top->type = MKOP(LOAD_VMX, 0, 16);\n \t\t\tbreak;\n \n \t\tcase 231:\t/* stvx */\n \t\tcase 487:\t/* stvxl */\n-\t\t\tif (!(regs->msr & MSR_VEC))\n-\t\t\t\tgoto vecunavail;\n \t\t\top->type = MKOP(STORE_VMX, 0, 16);\n \t\t\tbreak;\n #endif /* CONFIG_ALTIVEC */\n@@ -1584,29 +1580,21 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #ifdef CONFIG_PPC_FPU\n \t\tcase 535:\t/* lfsx */\n \t\tcase 567:\t/* lfsux */\n-\t\t\tif (!(regs->msr & MSR_FP))\n-\t\t\t\tgoto fpunavail;\n \t\t\top->type = MKOP(LOAD_FP, u, 4);\n \t\t\tbreak;\n \n \t\tcase 599:\t/* lfdx */\n \t\tcase 631:\t/* lfdux */\n-\t\t\tif (!(regs->msr & MSR_FP))\n-\t\t\t\tgoto fpunavail;\n \t\t\top->type = MKOP(LOAD_FP, u, 8);\n \t\t\tbreak;\n \n \t\tcase 663:\t/* stfsx */\n \t\tcase 695:\t/* stfsux */\n-\t\t\tif (!(regs->msr & MSR_FP))\n-\t\t\t\tgoto fpunavail;\n \t\t\top->type = MKOP(STORE_FP, u, 4);\n \t\t\tbreak;\n \n \t\tcase 727:\t/* stfdx */\n \t\tcase 759:\t/* stfdux */\n-\t\t\tif (!(regs->msr & MSR_FP))\n-\t\t\t\tgoto fpunavail;\n \t\t\top->type = MKOP(STORE_FP, u, 8);\n \t\t\tbreak;\n #endif\n@@ -1649,16 +1637,12 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #ifdef CONFIG_VSX\n \t\tcase 844:\t/* lxvd2x */\n \t\tcase 876:\t/* lxvd2ux */\n-\t\t\tif (!(regs->msr & MSR_VSX))\n-\t\t\t\tgoto vsxunavail;\n \t\t\top->reg = rd | ((instr & 1) << 5);\n \t\t\top->type = MKOP(LOAD_VSX, u, 16);\n \t\t\tbreak;\n \n \t\tcase 972:\t/* stxvd2x */\n \t\tcase 1004:\t/* stxvd2ux */\n-\t\t\tif (!(regs->msr & MSR_VSX))\n-\t\t\t\tgoto vsxunavail;\n \t\t\top->reg = rd | ((instr & 1) << 5);\n \t\t\top->type = MKOP(STORE_VSX, u, 16);\n \t\t\tbreak;\n@@ -1724,32 +1708,24 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n #ifdef CONFIG_PPC_FPU\n \tcase 48:\t/* lfs */\n \tcase 49:\t/* lfsu */\n-\t\tif (!(regs->msr & MSR_FP))\n-\t\t\tgoto fpunavail;\n \t\top->type = MKOP(LOAD_FP, u, 4);\n \t\top->ea = dform_ea(instr, regs);\n \t\tbreak;\n \n \tcase 50:\t/* lfd */\n \tcase 51:\t/* lfdu */\n-\t\tif (!(regs->msr & MSR_FP))\n-\t\t\tgoto fpunavail;\n \t\top->type = MKOP(LOAD_FP, u, 8);\n \t\top->ea = dform_ea(instr, regs);\n \t\tbreak;\n \n \tcase 52:\t/* stfs */\n \tcase 53:\t/* stfsu */\n-\t\tif (!(regs->msr & MSR_FP))\n-\t\t\tgoto fpunavail;\n \t\top->type = MKOP(STORE_FP, u, 4);\n \t\top->ea = dform_ea(instr, regs);\n \t\tbreak;\n \n \tcase 54:\t/* stfd */\n \tcase 55:\t/* stfdu */\n-\t\tif (!(regs->msr & MSR_FP))\n-\t\t\tgoto fpunavail;\n \t\top->type = MKOP(STORE_FP, u, 8);\n \t\top->ea = dform_ea(instr, regs);\n \t\tbreak;\n@@ -1812,24 +1788,6 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \top->type = INTERRUPT | 0x700;\n \top->val = SRR1_PROGTRAP;\n \treturn 0;\n-\n-#ifdef CONFIG_PPC_FPU\n- fpunavail:\n-\top->type = INTERRUPT | 0x800;\n-\treturn 0;\n-#endif\n-\n-#ifdef CONFIG_ALTIVEC\n- vecunavail:\n-\top->type = INTERRUPT | 0xf20;\n-\treturn 0;\n-#endif\n-\n-#ifdef CONFIG_VSX\n- vsxunavail:\n-\top->type = INTERRUPT | 0xf40;\n-\treturn 0;\n-#endif\n }\n EXPORT_SYMBOL_GPL(analyse_instr);\n NOKPROBE_SYMBOL(analyse_instr);\n@@ -2087,6 +2045,8 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \n #ifdef CONFIG_PPC_FPU\n \tcase LOAD_FP:\n+\t\tif (!(regs->msr & MSR_FP))\n+\t\t\treturn 0;\n \t\tif (size == 4)\n \t\t\terr = do_fp_load(op.reg, do_lfs, op.ea, size, regs);\n \t\telse\n@@ -2095,11 +2055,15 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase LOAD_VMX:\n+\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\treturn 0;\n \t\terr = do_vec_load(op.reg, do_lvx, op.ea & ~0xfUL, regs);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_VSX\n \tcase LOAD_VSX:\n+\t\tif (!(regs->msr & MSR_VSX))\n+\t\t\treturn 0;\n \t\terr = do_vsx_load(op.reg, do_lxvd2x, op.ea, regs);\n \t\tgoto ldst_done;\n #endif\n@@ -2134,6 +2098,8 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n \n #ifdef CONFIG_PPC_FPU\n \tcase STORE_FP:\n+\t\tif (!(regs->msr & MSR_FP))\n+\t\t\treturn 0;\n \t\tif (size == 4)\n \t\t\terr = do_fp_store(op.reg, do_stfs, op.ea, size, regs);\n \t\telse\n@@ -2142,11 +2108,15 @@ int emulate_step(struct pt_regs *regs, unsigned int instr)\n #endif\n #ifdef CONFIG_ALTIVEC\n \tcase STORE_VMX:\n+\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\treturn 0;\n \t\terr = do_vec_store(op.reg, do_stvx, op.ea & ~0xfUL, regs);\n \t\tgoto ldst_done;\n #endif\n #ifdef CONFIG_VSX\n \tcase STORE_VSX:\n+\t\tif (!(regs->msr & MSR_VSX))\n+\t\t\treturn 0;\n \t\terr = do_vsx_store(op.reg, do_stxvd2x, op.ea, regs);\n \t\tgoto ldst_done;\n #endif\n","prefixes":["v3","03/17"]}