{"id":807301,"url":"http://patchwork.ozlabs.org/api/1.0/patches/807301/?format=json","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.0/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":""},"msgid":"<20170829204934.9039-3-jsnow@redhat.com>","date":"2017-08-29T20:49:27","name":"[v2,2/9] IDE: Add register hints to tracing","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dedf03ba14c6cea1f1af0509cc224ac85942764f","submitter":{"id":64343,"url":"http://patchwork.ozlabs.org/api/1.0/people/64343/?format=json","name":"John Snow","email":"jsnow@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829204934.9039-3-jsnow@redhat.com/mbox/","series":[{"id":474,"url":"http://patchwork.ozlabs.org/api/1.0/series/474/?format=json","date":"2017-08-29T20:49:27","name":"IDE: replace printfs with tracing","version":2,"mbox":"http://patchwork.ozlabs.org/series/474/mbox/"}],"check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807301/checks/","tags":{},"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx02.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=jsnow@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhglC5Yrlz9sMN\n\tfor ;\n\tWed, 30 Aug 2017 06:50:47 +1000 (AEST)","from localhost ([::1]:46897 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dmnTB-0003sB-G8\n\tfor incoming@patchwork.ozlabs.org; Tue, 29 Aug 2017 16:50:45 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:50086)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dmnSG-0003by-G5\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:49:50 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dmnSF-0001un-00\n\tfor qemu-devel@nongnu.org; Tue, 29 Aug 2017 16:49:48 -0400","from mx1.redhat.com ([209.132.183.28]:47068)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dmnSA-0001rR-Pb; Tue, 29 Aug 2017 16:49:43 -0400","from smtp.corp.redhat.com\n\t(int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id B884C80C06;\n\tTue, 29 Aug 2017 20:49:41 +0000 (UTC)","from probe.bos.redhat.com (dhcp-17-231.bos.redhat.com\n\t[10.18.17.231])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id E998F62698;\n\tTue, 29 Aug 2017 20:49:40 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com B884C80C06","From":"John Snow ","To":"qemu-block@nongnu.org","Date":"Tue, 29 Aug 2017 16:49:27 -0400","Message-Id":"<20170829204934.9039-3-jsnow@redhat.com>","In-Reply-To":"<20170829204934.9039-1-jsnow@redhat.com>","References":"<20170829204934.9039-1-jsnow@redhat.com>","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.26]);\n\tTue, 29 Aug 2017 20:49:41 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PATCH v2 2/9] IDE: Add register hints to tracing","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"John Snow , qemu-devel@nongnu.org, f4bug@amsat.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"Name the registers for tracing purposes.\n\nSigned-off-by: John Snow \nReviewed-by: Eric Blake \n---\n hw/ide/core.c | 88 +++++++++++++++++++++++++++++++++++++++++------------\n hw/ide/trace-events | 8 ++---\n 2 files changed, 72 insertions(+), 24 deletions(-)","diff":"diff --git a/hw/ide/core.c b/hw/ide/core.c\nindex 31fd593..cb250e6 100644\n--- a/hw/ide/core.c\n+++ b/hw/ide/core.c\n@@ -1185,13 +1185,37 @@ static void ide_clear_hob(IDEBus *bus)\n bus->ifs[1].select &= ~(1 << 7);\n }\n \n+/* IOport [W]rite [R]egisters */\n+enum ATA_IOPORT_WR {\n+ ATA_IOPORT_WR_DATA = 0,\n+ ATA_IOPORT_WR_FEATURES = 1,\n+ ATA_IOPORT_WR_SECTOR_COUNT = 2,\n+ ATA_IOPORT_WR_SECTOR_NUMBER = 3,\n+ ATA_IOPORT_WR_CYLINDER_LOW = 4,\n+ ATA_IOPORT_WR_CYLINDER_HIGH = 5,\n+ ATA_IOPORT_WR_DEVICE_HEAD = 6,\n+ ATA_IOPORT_WR_COMMAND = 7,\n+ ATA_IOPORT_WR_NUM_REGISTERS,\n+};\n+\n+const char *ATA_IOPORT_WR_lookup[ATA_IOPORT_WR_NUM_REGISTERS] = {\n+ [ATA_IOPORT_WR_DATA] = \"Data\",\n+ [ATA_IOPORT_WR_FEATURES] = \"Features\",\n+ [ATA_IOPORT_WR_SECTOR_COUNT] = \"Sector Count\",\n+ [ATA_IOPORT_WR_SECTOR_NUMBER] = \"Sector Number\",\n+ [ATA_IOPORT_WR_CYLINDER_LOW] = \"Cylinder Low\",\n+ [ATA_IOPORT_WR_CYLINDER_HIGH] = \"Cylinder High\",\n+ [ATA_IOPORT_WR_DEVICE_HEAD] = \"Device/Head\",\n+ [ATA_IOPORT_WR_COMMAND] = \"Command\"\n+};\n+\n void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)\n {\n IDEBus *bus = opaque;\n IDEState *s = idebus_active_if(bus);\n int reg_num = addr & 7;\n \n- trace_ide_ioport_write(addr, val, bus, s);\n+ trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s);\n \n /* ignore writes to command block while busy with previous command */\n if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) {\n@@ -1201,43 +1225,43 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)\n switch (reg_num) {\n case 0:\n break;\n- case 1:\n-\tide_clear_hob(bus);\n+ case ATA_IOPORT_WR_FEATURES:\n+ ide_clear_hob(bus);\n /* NOTE: data is written to the two drives */\n-\tbus->ifs[0].hob_feature = bus->ifs[0].feature;\n-\tbus->ifs[1].hob_feature = bus->ifs[1].feature;\n+ bus->ifs[0].hob_feature = bus->ifs[0].feature;\n+ bus->ifs[1].hob_feature = bus->ifs[1].feature;\n bus->ifs[0].feature = val;\n bus->ifs[1].feature = val;\n break;\n- case 2:\n+ case ATA_IOPORT_WR_SECTOR_COUNT:\n \tide_clear_hob(bus);\n \tbus->ifs[0].hob_nsector = bus->ifs[0].nsector;\n \tbus->ifs[1].hob_nsector = bus->ifs[1].nsector;\n bus->ifs[0].nsector = val;\n bus->ifs[1].nsector = val;\n break;\n- case 3:\n+ case ATA_IOPORT_WR_SECTOR_NUMBER:\n \tide_clear_hob(bus);\n \tbus->ifs[0].hob_sector = bus->ifs[0].sector;\n \tbus->ifs[1].hob_sector = bus->ifs[1].sector;\n bus->ifs[0].sector = val;\n bus->ifs[1].sector = val;\n break;\n- case 4:\n+ case ATA_IOPORT_WR_CYLINDER_LOW:\n \tide_clear_hob(bus);\n \tbus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;\n \tbus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;\n bus->ifs[0].lcyl = val;\n bus->ifs[1].lcyl = val;\n break;\n- case 5:\n+ case ATA_IOPORT_WR_CYLINDER_HIGH:\n \tide_clear_hob(bus);\n \tbus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;\n \tbus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;\n bus->ifs[0].hcyl = val;\n bus->ifs[1].hcyl = val;\n break;\n- case 6:\n+ case ATA_IOPORT_WR_DEVICE_HEAD:\n \t/* FIXME: HOB readback uses bit 7 */\n bus->ifs[0].select = (val & ~0x10) | 0xa0;\n bus->ifs[1].select = (val | 0x10) | 0xa0;\n@@ -1245,7 +1269,7 @@ void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)\n bus->unit = (val >> 4) & 1;\n break;\n default:\n- case 7:\n+ case ATA_IOPORT_WR_COMMAND:\n /* command */\n ide_exec_cmd(bus, val);\n break;\n@@ -2052,6 +2076,30 @@ void ide_exec_cmd(IDEBus *bus, uint32_t val)\n }\n }\n \n+/* IOport [R]ead [R]egisters */\n+enum ATA_IOPORT_RR {\n+ ATA_IOPORT_RR_DATA = 0,\n+ ATA_IOPORT_RR_ERROR = 1,\n+ ATA_IOPORT_RR_SECTOR_COUNT = 2,\n+ ATA_IOPORT_RR_SECTOR_NUMBER = 3,\n+ ATA_IOPORT_RR_CYLINDER_LOW = 4,\n+ ATA_IOPORT_RR_CYLINDER_HIGH = 5,\n+ ATA_IOPORT_RR_DEVICE_HEAD = 6,\n+ ATA_IOPORT_RR_STATUS = 7,\n+ ATA_IOPORT_RR_NUM_REGISTERS,\n+};\n+\n+const char *ATA_IOPORT_RR_lookup[ATA_IOPORT_RR_NUM_REGISTERS] = {\n+ [ATA_IOPORT_RR_DATA] = \"Data\",\n+ [ATA_IOPORT_RR_ERROR] = \"Error\",\n+ [ATA_IOPORT_RR_SECTOR_COUNT] = \"Sector Count\",\n+ [ATA_IOPORT_RR_SECTOR_NUMBER] = \"Sector Number\",\n+ [ATA_IOPORT_RR_CYLINDER_LOW] = \"Cylinder Low\",\n+ [ATA_IOPORT_RR_CYLINDER_HIGH] = \"Cylinder High\",\n+ [ATA_IOPORT_RR_DEVICE_HEAD] = \"Device/Head\",\n+ [ATA_IOPORT_RR_STATUS] = \"Status\"\n+};\n+\n uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n {\n IDEBus *bus = opaque;\n@@ -2064,10 +2112,10 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n //hob = s->select & (1 << 7);\n hob = 0;\n switch (reg_num) {\n- case 0:\n+ case ATA_IOPORT_RR_DATA:\n ret = 0xff;\n break;\n- case 1:\n+ case ATA_IOPORT_RR_ERROR:\n if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||\n (s != bus->ifs && !s->blk)) {\n ret = 0;\n@@ -2077,7 +2125,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n \t ret = s->hob_feature;\n }\n break;\n- case 2:\n+ case ATA_IOPORT_RR_SECTOR_COUNT:\n if (!bus->ifs[0].blk && !bus->ifs[1].blk) {\n ret = 0;\n } else if (!hob) {\n@@ -2086,7 +2134,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n \t ret = s->hob_nsector;\n }\n break;\n- case 3:\n+ case ATA_IOPORT_RR_SECTOR_NUMBER:\n if (!bus->ifs[0].blk && !bus->ifs[1].blk) {\n ret = 0;\n } else if (!hob) {\n@@ -2095,7 +2143,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n \t ret = s->hob_sector;\n }\n break;\n- case 4:\n+ case ATA_IOPORT_RR_CYLINDER_LOW:\n if (!bus->ifs[0].blk && !bus->ifs[1].blk) {\n ret = 0;\n } else if (!hob) {\n@@ -2104,7 +2152,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n \t ret = s->hob_lcyl;\n }\n break;\n- case 5:\n+ case ATA_IOPORT_RR_CYLINDER_HIGH:\n if (!bus->ifs[0].blk && !bus->ifs[1].blk) {\n ret = 0;\n } else if (!hob) {\n@@ -2113,7 +2161,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n \t ret = s->hob_hcyl;\n }\n break;\n- case 6:\n+ case ATA_IOPORT_RR_DEVICE_HEAD:\n if (!bus->ifs[0].blk && !bus->ifs[1].blk) {\n ret = 0;\n } else {\n@@ -2121,7 +2169,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n }\n break;\n default:\n- case 7:\n+ case ATA_IOPORT_RR_STATUS:\n if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||\n (s != bus->ifs && !s->blk)) {\n ret = 0;\n@@ -2132,7 +2180,7 @@ uint32_t ide_ioport_read(void *opaque, uint32_t addr)\n break;\n }\n \n- trace_ide_ioport_read(addr, ret, bus, s);\n+ trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s);\n return ret;\n }\n \ndiff --git a/hw/ide/trace-events b/hw/ide/trace-events\nindex b9792812..bff8f39 100644\n--- a/hw/ide/trace-events\n+++ b/hw/ide/trace-events\n@@ -2,10 +2,10 @@\n \n # hw/ide/core.c\n # portio\n-ide_ioport_read(uint32_t addr, uint32_t val, void *bus, void *s) \"IDE PIO rd @ 0x%\"PRIx32\"; val 0x%02\"PRIx32\"; bus %p IDEState %p\"\n-ide_ioport_write(uint32_t addr, uint32_t val, void *bus, void *s) \"IDE PIO wr @ 0x%\"PRIx32\"; val 0x%02\"PRIx32\"; bus %p IDEState %p\"\n-ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) \"IDE PIO rd @ 0x%\"PRIx32\" (Alt Status); val 0x%02\"PRIx32\"; bus %p; IDEState %p\"\n-ide_cmd_write(uint32_t addr, uint32_t val, void *bus) \"IDE PIO wr @ 0x%\"PRIx32\" (Device Control); val 0x%02\"PRIx32\"; bus %p\"\n+ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) \"IDE PIO rd @ 0x%\"PRIx32\" (%s); val 0x%02\"PRIx32\"; bus %p IDEState %p\"\n+ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, void *s) \"IDE PIO wr @ 0x%\"PRIx32\" (%s); val 0x%02\"PRIx32\"; bus %p IDEState %p\"\n+ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) \"IDE PIO rd @ 0x%\"PRIx32\" (Alt Status); val 0x%02\"PRIx32\"; bus %p; IDEState %p\"\n+ide_cmd_write(uint32_t addr, uint32_t val, void *bus) \"IDE PIO wr @ 0x%\"PRIx32\" (Device Control); val 0x%02\"PRIx32\"; bus %p\"\n # misc\n ide_exec_cmd(void *bus, void *state, uint32_t cmd) \"IDE exec cmd: bus %p; state %p; cmd 0x%02x\"\n ide_cancel_dma_sync_buffered(void *fn, void *req) \"invoking cb %p of buffered request %p with -ECANCELED\"\n","prefixes":["v2","2/9"]}